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iverilog/ivtest/vvp_tests/real_negative_zero.json

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Add regression test for negative zero sign preservation Check that the vvp code generator emits a -0.0 real constant with its sign bit set, so the compiled value matches the runtime real value. The sign used to be detected with (value < 0), which is false for IEEE 754 -0.0, and a -0.0 constant was turned into +0.0. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-22 04:38:26 +02:00
{
"type" : "normal",
"source" : "real_negative_zero.v"
}