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Updated iCE40 PLL documentation (markdown)

Sylvain "tnt" Munaut 2024-04-01 15:45:01 +02:00
parent e87ef6806d
commit 5f433e2cc6
1 changed files with 5 additions and 5 deletions
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10
iCE40-PLL-documentation.md

@ -26,7 +26,7 @@ This must be done while the PLL is in reset (and so you can't depends on its out
Sequence would be : Sequence would be :
* Assert the reset of your logic clocked by any PLL output * Assert the reset of your logic clocked by any PLL output
* Assert `RESETB` (set to 0) * Assert `RESETB` (set to 0)
* Shift in new config word 1 bit at a time, MSB first. Data is shifted in on the rising edge of `SCLK` * Shift in new config word 1 bit at a time, MSB first. Data is shifted in on the falling edge of `SCLK`
* Release `RESETB` * Release `RESETB`
* Wait for `PLL_LOCK` * Wait for `PLL_LOCK`
* Release the reset of your logic clocked by PLL output * Release the reset of your logic clocked by PLL output
@ -53,8 +53,8 @@ The configuration word is 26 bits, or 27 bits for the UP5k :
* `1`: `PHASE_AND_DELAY` * `1`: `PHASE_AND_DELAY`
* `3`: `EXTERNAL` * `3`: `EXTERNAL`
* `pllout1Sel` and `pllout2Sel` are the output muxes * `pllout1Sel` and `pllout2Sel` are the output muxes
* `0`: `GENCLK` * `0`: `SHIFTREG_0deg`
* `1`: `GENCLK_HALF` * `1`: `SHIFTREG_90deg`
* `2`: `SHIFTREG_0deg` * `2`: `GENCLK`
* `3`: `SHIFTREG_90deg` * `3`: `GENCLK_HALF`