diff --git a/iCE40-PLL-documentation.md b/iCE40-PLL-documentation.md
index 9e6a23d..9c830ea 100644
--- a/iCE40-PLL-documentation.md
+++ b/iCE40-PLL-documentation.md
@@ -26,7 +26,7 @@ This must be done while the PLL is in reset (and so you can't depends on its out
 Sequence would be : 
 * Assert the reset of your logic clocked by any PLL output
 * Assert `RESETB` (set to 0)
-* Shift in new config word 1 bit at a time, MSB first. Data is shifted in on the rising edge of `SCLK`
+* Shift in new config word 1 bit at a time, MSB first. Data is shifted in on the falling edge of `SCLK`
 * Release `RESETB`
 * Wait for `PLL_LOCK`
 * Release the reset of your logic clocked by PLL output
@@ -53,8 +53,8 @@ The configuration word is 26 bits, or 27 bits for the UP5k :
     * `1`: `PHASE_AND_DELAY`
     * `3`: `EXTERNAL`
 * `pllout1Sel` and `pllout2Sel` are the output muxes
-    * `0`: `GENCLK`
-    * `1`: `GENCLK_HALF`
-    * `2`: `SHIFTREG_0deg`
-    * `3`: `SHIFTREG_90deg`
+    * `0`: `SHIFTREG_0deg`
+    * `1`: `SHIFTREG_90deg`
+    * `2`: `GENCLK`
+    * `3`: `GENCLK_HALF`