Clifford Wolf 2ccae0d386 Only dump memory initialization in icebox_vlog if present in ASC file, fixes #228 ...

Signed-off-by: Clifford Wolf <[email protected]>

2019-08-08 17:07:52 +02:00

..

.gitignore

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

icebox_asc2hlc.py

icebox_asc2hlc: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_chipdb.py

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

icebox_colbuf.py

icebox_colbuf: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_diff.py

icebox_diff: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_explain.py

icebox_explain: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_hlc2asc.py

icebox_hlc2asc: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_hlcsort.py

icebox_hlcsort: Adding a tool for canonicalizing HLC files.

2018-06-14 17:54:25 -07:00

icebox_html.py

icebox_html: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_maps.py

icebox_maps: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_stat.py

icebox_stat: Use cached re functions

2019-06-08 16:12:16 +02:00

icebox_vlog.py

Only dump memory initialization in icebox_vlog if present in ASC file, fixes #228

2019-08-08 17:07:52 +02:00

icebox.py

up5k: Fix TOPADDSUB_CARRYSELECT_0 override where it swaps with osc trimming

2019-07-03 12:54:00 +01:00

iceboxdb.py

Remove seperate 5k RAM DB and share with 8k instead

2018-01-16 15:17:20 +00:00

Makefile

iCE40 Ultra = iCE5LP = u4k port

2019-02-22 22:35:55 +01:00

tc_logic_xpr.py

icebox: Put .hlc converters under ISC license

2017-09-02 14:45:03 +02:00

tc_rxlat_netnames.py

icebox: Put .hlc converters under ISC license

2017-09-02 14:45:03 +02:00

tc_xlat_netnames.py

icebox: Put .hlc converters under ISC license

2017-09-02 14:45:03 +02:00