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.gitignore
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iCE40 Ultra = iCE5LP = u4k port
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2019-02-22 22:35:55 +01:00 |
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Makefile
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icebox: use $(PYTHON) variable in Makefile
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2019-10-22 14:09:15 +08:00 |
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icebox.py
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up5k: Fix TOPADDSUB_CARRYSELECT_0 override where it swaps with osc trimming
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2019-07-03 12:54:00 +01:00 |
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icebox_asc2hlc.py
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icebox_asc2hlc: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_chipdb.py
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iCE40 Ultra = iCE5LP = u4k port
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2019-02-22 22:35:55 +01:00 |
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icebox_colbuf.py
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icebox_colbuf: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_diff.py
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icebox_diff: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_explain.py
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icebox_explain: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_hlc2asc.py
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icebox_hlc2asc: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_hlcsort.py
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icebox_hlcsort: Adding a tool for canonicalizing HLC files.
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2018-06-14 17:54:25 -07:00 |
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icebox_html.py
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icebox_html: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_maps.py
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icebox_maps: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_stat.py
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icebox_stat: Use cached re functions
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2019-06-08 16:12:16 +02:00 |
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icebox_vlog.py
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Only dump memory initialization in icebox_vlog if present in ASC file, fixes #228
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2019-08-08 17:07:52 +02:00 |
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iceboxdb.py
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Remove seperate 5k RAM DB and share with 8k instead
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2018-01-16 15:17:20 +00:00 |
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tc_logic_xpr.py
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icebox: Put .hlc converters under ISC license
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2017-09-02 14:45:03 +02:00 |
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tc_rxlat_netnames.py
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icebox: Put .hlc converters under ISC license
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2017-09-02 14:45:03 +02:00 |
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tc_xlat_netnames.py
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icebox: Put .hlc converters under ISC license
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2017-09-02 14:45:03 +02:00 |
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