Clifford Wolf 70e01c1802 Add pre- and post-synthesis testbench examples		2017-07-18 18:38:01 +02:00
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.gitignore	Add pre- and post-synthesis testbench examples	2017-07-18 18:38:01 +02:00
Makefile	Add pre- and post-synthesis testbench examples	2017-07-18 18:38:01 +02:00
example.v	Some cleanups in verilog examples	2017-01-09 21:21:15 +01:00
icestick.pcf	Fixed files with CRLF line endings	2017-01-01 22:12:32 +01:00
rs232demo.v	Add pre- and post-synthesis testbench examples	2017-07-18 18:38:01 +02:00
rs232demo_tb.v	Add pre- and post-synthesis testbench examples	2017-07-18 18:38:01 +02:00