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icestorm
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Some cleanups in verilog examples

This commit is contained in:
Clifford Wolf 2017-01-09 21:21:15 +01:00
parent ff02cd753c
commit f920831e43
4 changed files with 4 additions and 4 deletions
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2
examples/hx8kboard/example.v
View File

@ -16,7 +16,7 @@ module top (
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always@(posedge clk) begin
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end

2
examples/iceblink/example.v
View File

@ -15,7 +15,7 @@ module top (
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always@(posedge clk) begin
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end

2
examples/icestick/example.v
View File

@ -13,7 +13,7 @@ module top (
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always@(posedge clk) begin
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end

2
examples/icezum/example.v
View File

@ -16,7 +16,7 @@ module top (
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always@(posedge clk) begin
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end