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2 Commits

Author SHA1 Message Date
Josh cf53448914
Merge bc9e33418d into 3cdcf4b009 2025-04-14 07:36:27 +00:00
Josh Heyse bc9e33418d
use raw strings for regex strings 2024-03-05 20:53:05 -06:00
4 changed files with 30 additions and 30 deletions

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@ -1258,21 +1258,21 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp4h_normalize(netname, "l") n = sp4h_normalize(netname, "l")
if n is not None: if n is not None:
if direction == "l" or is_ultra: if direction == "l" or is_ultra:
n = re_sub_cached("_l_", "_r_", n) n = re_sub_cached(r"_l_", "_r_", n)
n = sp4h_normalize(n) n = sp4h_normalize(n)
else: else:
n = re_sub_cached("_l_", "_", n) n = re_sub_cached(r"_l_", "_", n)
n = re_sub_cached("sp4_h_", "span4_horz_", n) n = re_sub_cached(r"sp4_h_", "span4_horz_", n)
return n return n
if m and direction in ("r", "R"): if m and direction in ("r", "R"):
n = sp4h_normalize(netname, "r") n = sp4h_normalize(netname, "r")
if n is not None: if n is not None:
if direction == "r" or is_ultra: if direction == "r" or is_ultra:
n = re_sub_cached("_r_", "_l_", n) n = re_sub_cached(r"_r_", "_l_", n)
n = sp4h_normalize(n) n = sp4h_normalize(n)
else: else:
n = re_sub_cached("_r_", "_", n) n = re_sub_cached(r"_r_", "_", n)
n = re_sub_cached("sp4_h_", "span4_horz_", n) n = re_sub_cached(r"sp4_h_", "span4_horz_", n)
return n return n
m = re_match_cached(r"sp4_v_[tb]_(\d+)$", netname) m = re_match_cached(r"sp4_v_[tb]_(\d+)$", netname)
@ -1280,25 +1280,25 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp4v_normalize(netname, "t") n = sp4v_normalize(netname, "t")
if n is not None: if n is not None:
if is_ultra and direction == "T" and pos in ("l", "r"): if is_ultra and direction == "T" and pos in ("l", "r"):
return re_sub_cached("sp4_v_", "span4_vert_", n) return re_sub_cached(r"sp4_v_", "span4_vert_", n)
elif direction == "t": elif direction == "t":
n = re_sub_cached("_t_", "_b_", n) n = re_sub_cached(r"_t_", "_b_", n)
n = sp4v_normalize(n) n = sp4v_normalize(n)
else: else:
n = re_sub_cached("_t_", "_", n) n = re_sub_cached(r"_t_", "_", n)
n = re_sub_cached("sp4_v_", "span4_vert_", n) n = re_sub_cached(r"sp4_v_", "span4_vert_", n)
return n return n
if m and direction in ("b", "B"): if m and direction in ("b", "B"):
n = sp4v_normalize(netname, "b") n = sp4v_normalize(netname, "b")
if n is not None: if n is not None:
if is_ultra and direction == "B" and pos in ("l", "r"): if is_ultra and direction == "B" and pos in ("l", "r"):
return re_sub_cached("sp4_v_", "span4_vert_", n) return re_sub_cached(r"sp4_v_", "span4_vert_", n)
elif direction == "b": elif direction == "b":
n = re_sub_cached("_b_", "_t_", n) n = re_sub_cached(r"_b_", "_t_", n)
n = sp4v_normalize(n) n = sp4v_normalize(n)
else: else:
n = re_sub_cached("_b_", "_", n) n = re_sub_cached(r"_b_", "_", n)
n = re_sub_cached("sp4_v_", "span4_vert_", n) n = re_sub_cached(r"sp4_v_", "span4_vert_", n)
return n return n
m = re_match_cached(r"sp12_h_[lr]_(\d+)$", netname) m = re_match_cached(r"sp12_h_[lr]_(\d+)$", netname)
@ -1306,21 +1306,21 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp12h_normalize(netname, "l") n = sp12h_normalize(netname, "l")
if n is not None: if n is not None:
if direction == "l" or is_ultra: if direction == "l" or is_ultra:
n = re_sub_cached("_l_", "_r_", n) n = re_sub_cached(r"_l_", "_r_", n)
n = sp12h_normalize(n) n = sp12h_normalize(n)
else: else:
n = re_sub_cached("_l_", "_", n) n = re_sub_cached(r"_l_", "_", n)
n = re_sub_cached("sp12_h_", "span12_horz_", n) n = re_sub_cached(r"sp12_h_", "span12_horz_", n)
return n return n
if m and direction in ("r", "R"): if m and direction in ("r", "R"):
n = sp12h_normalize(netname, "r") n = sp12h_normalize(netname, "r")
if n is not None: if n is not None:
if direction == "r" or is_ultra: if direction == "r" or is_ultra:
n = re_sub_cached("_r_", "_l_", n) n = re_sub_cached(r"_r_", "_l_", n)
n = sp12h_normalize(n) n = sp12h_normalize(n)
else: else:
n = re_sub_cached("_r_", "_", n) n = re_sub_cached(r"_r_", "_", n)
n = re_sub_cached("sp12_h_", "span12_horz_", n) n = re_sub_cached(r"sp12_h_", "span12_horz_", n)
return n return n
m = re_match_cached(r"sp12_v_[tb]_(\d+)$", netname) m = re_match_cached(r"sp12_v_[tb]_(\d+)$", netname)
@ -1328,25 +1328,25 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp12v_normalize(netname, "t") n = sp12v_normalize(netname, "t")
if n is not None: if n is not None:
if direction == "t": if direction == "t":
n = re_sub_cached("_t_", "_b_", n) n = re_sub_cached(r"_t_", "_b_", n)
n = sp12v_normalize(n) n = sp12v_normalize(n)
elif direction == "T" and pos in ("l", "r"): elif direction == "T" and pos in ("l", "r"):
pass pass
else: else:
n = re_sub_cached("_t_", "_", n) n = re_sub_cached(r"_t_", "_", n)
n = re_sub_cached("sp12_v_", "span12_vert_", n) n = re_sub_cached(r"sp12_v_", "span12_vert_", n)
return n return n
if m and direction in ("b", "B"): if m and direction in ("b", "B"):
n = sp12v_normalize(netname, "b") n = sp12v_normalize(netname, "b")
if n is not None: if n is not None:
if direction == "b": if direction == "b":
n = re_sub_cached("_b_", "_t_", n) n = re_sub_cached(r"_b_", "_t_", n)
n = sp12v_normalize(n) n = sp12v_normalize(n)
elif direction == "B" and pos in ("l", "r"): elif direction == "B" and pos in ("l", "r"):
pass pass
else: else:
n = re_sub_cached("_b_", "_", n) n = re_sub_cached(r"_b_", "_", n)
n = re_sub_cached("sp12_v_", "span12_vert_", n) n = re_sub_cached(r"sp12_v_", "span12_vert_", n)
return n return n
if (pos in ("l", "r" )) and (not is_ultra): if (pos in ("l", "r" )) and (not is_ultra):

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@ -509,7 +509,7 @@ def parse_verilog_bitvector_to_bits(in_str):
#replace x with 0 #replace x with 0
in_str = re_sub_cached('[xX]', '0', in_str) in_str = re_sub_cached('[xX]', '0', in_str)
m = re_match_cached("([0-9]+)'([hdob])([0-9a-fA-F]+)", in_str) m = re_match_cached(r"([0-9]+)'([hdob])([0-9a-fA-F]+)", in_str)
if m: if m:
num_bits = int(m.group(1)) num_bits = int(m.group(1))
prefix = m.group(2) prefix = m.group(2)
@ -879,7 +879,7 @@ class LogicCell:
if fields[0] == 'lut' and len(fields) == 2: if fields[0] == 'lut' and len(fields) == 2:
self.lut_bits = fields[1] self.lut_bits = fields[1]
elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=': elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=':
m = re_match_cached("([0-9]+)'b([01]+)", fields[2]) m = re_match_cached(r"([0-9]+)'b([01]+)", fields[2])
if m: if m:
lut_bits = parse_verilog_bitvector_to_bits(fields[2]) lut_bits = parse_verilog_bitvector_to_bits(fields[2])
# Verilog 16'bXXXX is MSB first but the bitstream wants LSB. # Verilog 16'bXXXX is MSB first but the bitstream wants LSB.

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@ -60,7 +60,7 @@ def get_bit_group(x, y, db):
funcs.add("r") funcs.add("r")
elif entry[1] == "buffer": elif entry[1] == "buffer":
funcs.add("b") funcs.add("b")
elif re_match_cached("LC_", entry[1]): elif re_match_cached(r"LC_", entry[1]):
funcs.add("l") funcs.add("l")
elif entry[1] == "NegClk": elif entry[1] == "NegClk":
funcs.add("N") funcs.add("N")

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@ -94,7 +94,7 @@ for o, a in opts:
elif o in ("-p", "-P"): elif o in ("-p", "-P"):
with open(a, "r") as f: with open(a, "r") as f:
for line in f: for line in f:
if o == "-P" and not re_search_cached(" # ICE_(GB_)?IO", line): if o == "-P" and not re_search_cached(r" # ICE_(GB_)?IO", line):
continue continue
line = re_sub_cached(r"#.*", "", line.strip()).split() line = re_sub_cached(r"#.*", "", line.strip()).split()
if "--warn-no-port" in line: if "--warn-no-port" in line: