Compare commits

...

7 Commits

Author SHA1 Message Date
Josh b5e023ee24
Merge bc9e33418d into f31c39cc2e 2025-06-15 14:22:32 +05:30
Miodrag Milanović f31c39cc2e
Merge pull request #342 from tarikgraba/master
Settings to build pdf documentation
2025-06-03 14:40:39 +02:00
TG 213d116050 Use Lualatex instead of plain pdfatex 2025-06-03 14:30:45 +02:00
TG 8893d13655 Use rsvgconverter sphinx extension to convert svg to pdf 2025-06-03 14:30:45 +02:00
Miodrag Milanović 0bd9f5d7fa
Merge pull request #348 from mattvenn/master
Update Claire's name and fix the reference image in the iceprog help
2025-06-03 11:12:06 +02:00
Matt Venn d06a967590 Update Claire's name and fix the reference image in the iceprog help 2025-06-03 11:06:08 +02:00
Josh Heyse bc9e33418d
use raw strings for regex strings 2024-03-05 20:53:05 -06:00
22 changed files with 58 additions and 54 deletions

View File

@ -55,9 +55,8 @@ further defined and clarified by project maintainers.
Enforcement
Instances of abusive, harassing, or otherwise unacceptable behavior may be
reported by contacting the project team at clifford@clifford.at (and/or
cliffordvienna@gmail.com if you think your mail to the other address got
stuck in the spam filter). All complaints will be reviewed and investigated and
reported by contacting the project team at office@yosyshq.com.
All complaints will be reviewed and investigated and
will result in a response that is deemed necessary and appropriate to the
circumstances. The project team is obligated to maintain confidentiality with
regard to the reporter of an incident. Further details of specific enforcement

Binary file not shown.

After

Width:  |  Height:  |  Size: 1.8 MiB

View File

@ -13,7 +13,9 @@ author = 'YosysHQ'
# -- General configuration ---------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
extensions = ['sphinx_rtd_theme']
extensions = ['sphinx_rtd_theme',
'sphinxcontrib.rsvgconverter'
]
templates_path = ['_templates']
exclude_patterns = []
@ -31,3 +33,5 @@ html_theme_options = {
"titles_only": False
}
html_static_path = ['_static']
latex_engine = 'lualatex'

View File

@ -1,2 +1,3 @@
sphinx
sphinx_rtd_theme
sphinxcontrib-svg2pdfconverter

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
@ -1258,21 +1258,21 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp4h_normalize(netname, "l")
if n is not None:
if direction == "l" or is_ultra:
n = re_sub_cached("_l_", "_r_", n)
n = re_sub_cached(r"_l_", "_r_", n)
n = sp4h_normalize(n)
else:
n = re_sub_cached("_l_", "_", n)
n = re_sub_cached("sp4_h_", "span4_horz_", n)
n = re_sub_cached(r"_l_", "_", n)
n = re_sub_cached(r"sp4_h_", "span4_horz_", n)
return n
if m and direction in ("r", "R"):
n = sp4h_normalize(netname, "r")
if n is not None:
if direction == "r" or is_ultra:
n = re_sub_cached("_r_", "_l_", n)
n = re_sub_cached(r"_r_", "_l_", n)
n = sp4h_normalize(n)
else:
n = re_sub_cached("_r_", "_", n)
n = re_sub_cached("sp4_h_", "span4_horz_", n)
n = re_sub_cached(r"_r_", "_", n)
n = re_sub_cached(r"sp4_h_", "span4_horz_", n)
return n
m = re_match_cached(r"sp4_v_[tb]_(\d+)$", netname)
@ -1280,25 +1280,25 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp4v_normalize(netname, "t")
if n is not None:
if is_ultra and direction == "T" and pos in ("l", "r"):
return re_sub_cached("sp4_v_", "span4_vert_", n)
return re_sub_cached(r"sp4_v_", "span4_vert_", n)
elif direction == "t":
n = re_sub_cached("_t_", "_b_", n)
n = re_sub_cached(r"_t_", "_b_", n)
n = sp4v_normalize(n)
else:
n = re_sub_cached("_t_", "_", n)
n = re_sub_cached("sp4_v_", "span4_vert_", n)
n = re_sub_cached(r"_t_", "_", n)
n = re_sub_cached(r"sp4_v_", "span4_vert_", n)
return n
if m and direction in ("b", "B"):
n = sp4v_normalize(netname, "b")
if n is not None:
if is_ultra and direction == "B" and pos in ("l", "r"):
return re_sub_cached("sp4_v_", "span4_vert_", n)
return re_sub_cached(r"sp4_v_", "span4_vert_", n)
elif direction == "b":
n = re_sub_cached("_b_", "_t_", n)
n = re_sub_cached(r"_b_", "_t_", n)
n = sp4v_normalize(n)
else:
n = re_sub_cached("_b_", "_", n)
n = re_sub_cached("sp4_v_", "span4_vert_", n)
n = re_sub_cached(r"_b_", "_", n)
n = re_sub_cached(r"sp4_v_", "span4_vert_", n)
return n
m = re_match_cached(r"sp12_h_[lr]_(\d+)$", netname)
@ -1306,21 +1306,21 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp12h_normalize(netname, "l")
if n is not None:
if direction == "l" or is_ultra:
n = re_sub_cached("_l_", "_r_", n)
n = re_sub_cached(r"_l_", "_r_", n)
n = sp12h_normalize(n)
else:
n = re_sub_cached("_l_", "_", n)
n = re_sub_cached("sp12_h_", "span12_horz_", n)
n = re_sub_cached(r"_l_", "_", n)
n = re_sub_cached(r"sp12_h_", "span12_horz_", n)
return n
if m and direction in ("r", "R"):
n = sp12h_normalize(netname, "r")
if n is not None:
if direction == "r" or is_ultra:
n = re_sub_cached("_r_", "_l_", n)
n = re_sub_cached(r"_r_", "_l_", n)
n = sp12h_normalize(n)
else:
n = re_sub_cached("_r_", "_", n)
n = re_sub_cached("sp12_h_", "span12_horz_", n)
n = re_sub_cached(r"_r_", "_", n)
n = re_sub_cached(r"sp12_h_", "span12_horz_", n)
return n
m = re_match_cached(r"sp12_v_[tb]_(\d+)$", netname)
@ -1328,25 +1328,25 @@ def pos_follow_net(pos, direction, netname, is_ultra):
n = sp12v_normalize(netname, "t")
if n is not None:
if direction == "t":
n = re_sub_cached("_t_", "_b_", n)
n = re_sub_cached(r"_t_", "_b_", n)
n = sp12v_normalize(n)
elif direction == "T" and pos in ("l", "r"):
pass
else:
n = re_sub_cached("_t_", "_", n)
n = re_sub_cached("sp12_v_", "span12_vert_", n)
n = re_sub_cached(r"_t_", "_", n)
n = re_sub_cached(r"sp12_v_", "span12_vert_", n)
return n
if m and direction in ("b", "B"):
n = sp12v_normalize(netname, "b")
if n is not None:
if direction == "b":
n = re_sub_cached("_b_", "_t_", n)
n = re_sub_cached(r"_b_", "_t_", n)
n = sp12v_normalize(n)
elif direction == "B" and pos in ("l", "r"):
pass
else:
n = re_sub_cached("_b_", "_", n)
n = re_sub_cached("sp12_v_", "span12_vert_", n)
n = re_sub_cached(r"_b_", "_", n)
n = re_sub_cached(r"sp12_v_", "span12_vert_", n)
return n
if (pos in ("l", "r" )) and (not is_ultra):

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above

View File

@ -509,7 +509,7 @@ def parse_verilog_bitvector_to_bits(in_str):
#replace x with 0
in_str = re_sub_cached('[xX]', '0', in_str)
m = re_match_cached("([0-9]+)'([hdob])([0-9a-fA-F]+)", in_str)
m = re_match_cached(r"([0-9]+)'([hdob])([0-9a-fA-F]+)", in_str)
if m:
num_bits = int(m.group(1))
prefix = m.group(2)
@ -879,7 +879,7 @@ class LogicCell:
if fields[0] == 'lut' and len(fields) == 2:
self.lut_bits = fields[1]
elif fields[0] == 'out' and len(fields) >= 3 and fields[1] == '=':
m = re_match_cached("([0-9]+)'b([01]+)", fields[2])
m = re_match_cached(r"([0-9]+)'b([01]+)", fields[2])
if m:
lut_bits = parse_verilog_bitvector_to_bits(fields[2])
# Verilog 16'bXXXX is MSB first but the bitstream wants LSB.

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
@ -60,7 +60,7 @@ def get_bit_group(x, y, db):
funcs.add("r")
elif entry[1] == "buffer":
funcs.add("b")
elif re_match_cached("LC_", entry[1]):
elif re_match_cached(r"LC_", entry[1]):
funcs.add("l")
elif entry[1] == "NegClk":
funcs.add("N")

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above

View File

@ -1,6 +1,6 @@
#!/usr/bin/env python3
#
# Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
# Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
@ -94,7 +94,7 @@ for o, a in opts:
elif o in ("-p", "-P"):
with open(a, "r") as f:
for line in f:
if o == "-P" and not re_search_cached(" # ICE_(GB_)?IO", line):
if o == "-P" and not re_search_cached(r" # ICE_(GB_)?IO", line):
continue
line = re_sub_cached(r"#.*", "", line.strip()).split()
if "--warn-no-port" in line:

View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2016 Clifford Wolf <clifford@clifford.at>
// Copyright (C) 2016 Claire Xenia Wolf <claire@clairexen.net>
// Copyright (C) 2023 Sylvain Munaut <tnt@246tNt.com>
//
// Permission to use, copy, modify, and/or distribute this software for any

View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
// Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
//
// Based on a reference implementation provided by Mathias Lasser
//

View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
// Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above

View File

@ -1,7 +1,7 @@
/*
* iceprog -- simple programming tool for FTDI-based Lattice iCE programmers
*
* Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
* Copyright (C) 2018 Piotr Esden-Tempski <piotr@esden.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
@ -549,14 +549,14 @@ static void help(const char *progname)
fprintf(stderr, " programming the flash chip and one zero ohm resistor must be desoldered\n");
fprintf(stderr, " and the FT2232H SI pin must be connected to the iCE SPI_SI pin, as shown\n");
fprintf(stderr, " in this picture:\n");
fprintf(stderr, " http://www.clifford.at/gallery/2014-elektronik/IMG_20141115_183838\n");
fprintf(stderr, " https://github.com/yosyshq/icestorm/blob/master/docs/source/_static/images/icestick.jpg\n");
fprintf(stderr, "\n");
fprintf(stderr, "Notes for the iCE40-HX8K Breakout Board:\n");
fprintf(stderr, " Make sure that the jumper settings on the board match the selected\n");
fprintf(stderr, " mode (SRAM or FLASH). See the iCE40-HX8K user manual for details.\n");
fprintf(stderr, "\n");
fprintf(stderr, "If you have a bug report, please file an issue on github:\n");
fprintf(stderr, " https://github.com/cliffordwolf/icestorm/issues\n");
fprintf(stderr, " https://github.com/YosysHQ/icestorm/issues\n");
}
int main(int argc, char **argv)

View File

@ -1,7 +1,7 @@
/*
* iceprog -- simple programming tool for FTDI-based Lattice iCE programmers
*
* Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
* Copyright (C) 2018 Piotr Esden-Tempski <piotr@esden.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
@ -360,4 +360,4 @@ void mpsse_close(void)
ftdi_disable_bitbang(&mpsse_ftdic);
ftdi_usb_close(&mpsse_ftdic);
ftdi_deinit(&mpsse_ftdic);
}
}

View File

@ -1,7 +1,7 @@
/*
* iceprog -- simple programming tool for FTDI-based Lattice iCE programmers
*
* Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
* Copyright (C) 2018 Piotr Esden-Tempski <piotr@esden.net>
*
* Permission to use, copy, modify, and/or distribute this software for any

View File

@ -1,5 +1,5 @@
//
// Copyright (C) 2015 Clifford Wolf <clifford@clifford.at>
// Copyright (C) 2015 Claire Xenia Wolf <claire@clairexen.net>
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above

View File

@ -1,7 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2012 Claire Xenia Wolf <claire@clairexen.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above