20 Commits

Author	SHA1	Message	Date
David Shah	a59472812c	Remove seperate 5k RAM DB and share with 8k instead ... This should ensure that the 5k RAM routing entries are now complete, fixing #115	2018-01-16 15:17:20 +00:00
David Shah	614c60df25	Add missing 5k BRAM bits	2017-11-17 18:29:14 +00:00
David Shah	94aa596cb1	Trace DSP routing	2017-11-17 15:08:25 +00:00
David Shah	5e7924c8c1	Add more 5k RAM bits to db	2017-11-05 19:14:42 +00:00
David Shah	e9e9d0e9cb	Share glb_netwk data between 5k and 8k parts	2017-10-29 16:14:15 +00:00
David Shah	2a7c32e49a	Add ColBufCtrl bits to database for 5k parts	2017-10-25 10:50:36 +01:00
David Shah	5afdeee0e0	Swap IEREN for pin 26 to get example working, other inputs still need fixing	2017-10-21 20:16:10 +01:00
David Shah	ca35e566d4	Modify icebox.py so it generates a 5k chipdb	2017-10-20 19:13:23 +01:00
Clifford Wolf	72d2a02810	Remove extra IoCtrl cf_bit_ and extra_padeb_test_ lines from database	2017-07-31 15:55:07 +02:00
Scott Shawcroft	f16265c662	Work in progress DB. Having trouble getting group_segments to work without error.	2017-07-07 16:50:11 -07:00
Clifford Wolf	92d3ea0e58	icefuzz improvements, refuzz timings	2016-01-16 16:17:56 +01:00
Clifford Wolf	2fe704227f	Fuzzed RamCascade bits	2016-01-09 12:45:43 +01:00
Clifford Wolf	9c9983cff8	Added lutff_i/lout net to model	2015-12-04 11:46:08 +01:00
Clifford Wolf	d72b6d41bd	Added 8k timing data	2015-10-06 09:12:26 +02:00
Clifford Wolf	11518976f3	more database updates	2015-10-02 14:06:24 +02:00
Clifford Wolf	723e41d598	database updates	2015-09-27 20:11:30 +02:00
Clifford Wolf	48154cb6f4	Imported full dev sources	2015-07-18 13:10:40 +02:00
Clifford Wolf	13e63e6b65	Import of icestorm-snapshot-150526.zip	2015-07-18 13:07:39 +02:00
Clifford Wolf	c41701ca3a	Import of icestorm-snapshot-150413.zip	2015-07-18 13:06:48 +02:00
Clifford Wolf	dfeb92a46b	Import of icestorm-snapshot-150322.zip	2015-07-18 13:05:02 +02:00