icetime progress

icetime/icetime.cc

@@ -828,6 +828,8 @@ void make_seg_cell(int net, const net_segment_t &seg)
 			netlist_cells[cell][seg.name.substr(4)] = net_name(net);
 			if (seg.name == "ram/RCLK" || seg.name == "ram/WCLK")
 				make_inmux(seg.x, seg.y, net, "ClkMux");
+			else if (seg.name == "ram/RCLKE" || seg.name == "ram/WCLKE")
+				make_inmux(seg.x, seg.y, net, "CEMux");
 			else
 				make_inmux(seg.x, seg.y, net, "SRMux");
 		}
@@ -1354,6 +1356,58 @@ int main(int argc, char **argv)
 	for (auto &seg : net_to_segments[net])
 		make_seg_cell(net, seg);
 
+	for (int x = 0; x < int(config_tile_type.size()); x++)
+	for (int y = 0; y < int(config_tile_type[x].size()); y++)
+	{
+		auto const &tile_type = config_tile_type[x][y];
+
+		if (tile_type == "ramb")
+		{
+			bool cascade_cbits[4] = {false, false, false, false};
+			bool &cascade_cbit_4 = cascade_cbits[0];
+			// bool &cascade_cbit_5 = cascade_cbits[1];
+			bool &cascade_cbit_6 = cascade_cbits[2];
+			// bool &cascade_cbit_7 = cascade_cbits[3];
+			std::pair<int, int> bitpos;
+
+			for (int i = 0; i < 4; i++) {
+				std::string cbit_name = stringf("RamCascade.CBIT_%d", i+4);
+				if (ramb_tile_bits.count(cbit_name)) {
+					bitpos = ramb_tile_bits.at(cbit_name)[0];
+					cascade_cbits[i] = config_bits[x][y][bitpos.first][bitpos.second];
+				}
+				if (ramt_tile_bits.count(cbit_name)) {
+					bitpos = ramt_tile_bits.at(cbit_name)[0];
+					cascade_cbits[i] = config_bits[x][y+1][bitpos.first][bitpos.second];
+				}
+			}
+
+			if (cascade_cbit_4 && cascade_cbit_6)
+			{
+				std::string src_cell = stringf("ram_%d_%d", x, y+2);
+				std::string dst_cell = stringf("ram_%d_%d", x, y);
+
+				for (int rw = 0; rw < 2; rw++)
+				for (int i = 0; i < 11; i++)
+				{
+					std::string port = stringf("%cADDR[%d]", rw ? 'R' : 'W', i);
+
+					if (netlist_cells[src_cell][port] == "")
+						continue;
+
+					std::string srcnet = netlist_cells[src_cell][port];
+					std::string tmpnet = tname();
+					extra_wires.insert(tmpnet);
+
+					extra_vlog.push_back(stringf("  CascadeBuf %s (.I(%s), .O(%s));\n",
+							tname().c_str(), srcnet.c_str(), tmpnet.c_str()));
+
+					netlist_cells[dst_cell][port] = cascademuxed(tmpnet);
+				}
+			}
+		}
+	}
+
 	FILE *graph_f = nullptr;
 
 	if (!graph_nets.empty())

icetime/mktest.py

@@ -70,6 +70,62 @@ with open("%s.v" % sys.argv[1], "w") as f:
             end
           endmodule
         """, file=f)
+    if mode == "test4":
+        io_names = [ "clk", "i", "s", "o" ]
+        print("""
+          module top(input clk, i, s, output reg o);
+            reg re1, rclke1, we1, wclke1;
+            reg [7:0] raddr1, waddr1;
+            reg [15:0] rdata1, wdata1, mask1;
+            wire [15:0] rdata1_unreg;
+
+            reg re2, rclke2, we2, wclke2;
+            reg [7:0] raddr2, waddr2;
+            reg [15:0] rdata2, wdata2, mask2;
+            wire [15:0] rdata2_unreg;
+
+            always @(posedge clk) begin
+              o <= rdata1[15];
+              {rdata1, rdata2} <= {rdata1, rdata2} << 1;
+              {raddr1, waddr1, wdata1, mask1, re1, rclke1, we1, wclke1,
+               raddr2, waddr2, wdata2, mask2, re2, rclke2, we2, wclke2} <=
+                ({raddr1, waddr1, wdata1, mask1, re1, rclke1, we1, wclke1,
+                  raddr2, waddr2, wdata2, mask2, re2, rclke2, we2, wclke2} << 1) | i;
+              if (s) begin
+                rdata1 <= rdata1_unreg;
+                rdata2 <= rdata2_unreg;
+              end
+            end
+
+            SB_RAM40_4K mem1 (
+              .RDATA(rdata1_unreg),
+              .RCLK(clk),
+              .RCLKE(rclke1),
+              .RE(re1),
+              .RADDR(raddr1),
+              .WCLK(clk),
+              .WCLKE(wclke1),
+              .WE(we1),
+              .WADDR(waddr1),
+              .MASK(mask1),
+              .WDATA(wdata1)
+            );
+
+            SB_RAM40_4K mem2 (
+              .RDATA(rdata2_unreg),
+              .RCLK(clk),
+              .RCLKE(rclke2),
+              .RE(re2),
+              .RADDR(raddr1), // <- cascade
+              .WCLK(clk),
+              .WCLKE(wclke2),
+              .WE(we2),
+              .WADDR(waddr1), // <- cascade
+              .MASK(mask2),
+              .WDATA(wdata2)
+            );
+          endmodule
+        """, file=f)
 
 with open("%s.pcf" % sys.argv[1], "w") as f:
     for i, name in enumerate(io_names):
@@ -94,6 +150,9 @@ with open("%s.ys" % sys.argv[1], "w") as f:
 assert os.system("bash ../icefuzz/icecube.sh %s.v" % sys.argv[1]) == 0
 os.rename("%s.v" % sys.argv[1], "%s_in.v" % sys.argv[1])
 
+if False:
+    assert os.system("python3 ../icebox/icebox_explain.py %s.asc > %s.ex" % (sys.argv[1], sys.argv[1])) == 0
+
 with open("%s_ref.v" % sys.argv[1], "w") as f:
     for line in open("%s.vsb" % sys.argv[1], "r"):
         if re.match(r" *defparam .*\.(IO_STANDARD|PULLUP|INIT_.|WRITE_MODE|READ_MODE)=", line):