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<p> <p>
Project IceStorm aims at reverse engineering and documenting the bitstream Project IceStorm aims at reverse engineering and documenting the bitstream
format of Lattice iCE40 FPGAs and providing simple tools for analyzing and format of Lattice iCE40 FPGAs and providing simple tools for analyzing and
creating bitstream files. At the moment the focus of the project is on the creating bitstream files. The focus of the project is on the iCE40 1K and
HX1K-TQ144 and HX8K-CT256 devices, but most of the information is 8K chips. (Most of the work was done on HX1K-TQ144 and HX8K-CT256 parts.)
device-independent.
</p> </p>
<h2>Why the Lattice iCE40?</h2> <h2>Why the Lattice iCE40?</h2>
@ -32,23 +31,25 @@ reverse engineering and as a reference platform for general purpose FPGA tool de
</p> </p>
<p> <p>
Also, with the <a href="http://www.latticesemi.com/icestick">iCEstick</a> there is Also, with the <a href="http://www.latticesemi.com/icestick">Lattice iCEstick</a> there is
a cheap and easy to use development platform available, which makes the part interesting a cheap and easy to use development platform available, which makes the part interesting
for all kinds of projects. for all kinds of projects. (The iCEstick features an HX1K device. Lattice also sells an <a
href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">iCE40-HX8K
Breakout Board</a> featuring an HX8K chip.)
</p> </p>
<h2>What is the Status of the Project?</h2> <h2>What is the Status of the Project?</h2>
<p> <p>
We have enough bits mapped that we can create a functional Verilog model for We are pretty confident that we have the 1K and 8K devices completely reverse
almost all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144 engineered. For example, it seems we can create correct functional Verilog
and the iCE40 HX8K-CT256, and can create bitstreams for this parts using our models for all bitstreams generated by Lattice iCEcube2 for the iCE40
own tool-chain. HX1K-TQ144 and the iCE40 HX8K-CT256 using our <tt>icebox_vlog</tt> tool.
</p> </p>
<p> <p>
The next milestones for the project are timing analysis and support for more Current work focuses on improvements in our timing analysis flow and support
parts from the iCE40 family. for all iCE40 LP/HX 1K, 4K, and 8K devices.
</p> </p>
<h2>What is the Status of the Fully Open Source iCE40 Flow?</h2> <h2>What is the Status of the Fully Open Source iCE40 Flow?</h2>
@ -66,6 +67,12 @@ arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc
icepack rot.asc rot.bin icepack rot.asc rot.bin
iceprog rot.bin</pre> iceprog rot.bin</pre>
<p>
A simple timing analysis report can be generated using the <tt>icetime</tt> utility:
</p>
<pre style="padding-left: 3em">icetime -tmd hx1k rot.asc</pre>
<h2>Where are the Tools? How to install?</h2> <h2>Where are the Tools? How to install?</h2>
<p> <p>
@ -125,25 +132,34 @@ share regarding the install procedures on the operating system of your choice.
<h2>What are the IceStorm Tools?</h2> <h2>What are the IceStorm Tools?</h2>
<p>
The IceStorm Tools are a couple of small programs for working with iCE40 bitstream files and our
ASCII representation of it. The complete Open Source iCE40 Flow consists of the <a
href="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a>, <a
href="https://github.com/cseed/arachne-pnr">Arachne-PNR</a>, and <a
href="http://www.clifford.at/yosys/">Yosys</a>.
</p>
<h3>IcePack/IceUnpack</h3> <h3>IcePack/IceUnpack</h3>
<p> <p>
The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceBox ASCII format The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceStorm ASCII format
that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The
<span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file. <span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file. All
other IceStorm Tools operate on the ASCII file format, not the bitstream binaries.
</p> </p>
<h3>IceTime</h3> <h3>IceTime</h3>
<p> <p>
The <span style="font-family:monospace">icetime</span> program is an iCE40 timing analysis tool. It reads designs in IceBox ASCII format and writes times timing The <span style="font-family:monospace">icetime</span> program is an iCE40 timing analysis tool. It reads designs in IceStorm ASCII format and writes times timing
netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports. netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports.
</p> </p>
<h3>IceBox</h3> <h3>IceBox</h3>
<p> <p>
A python library and various tools for working with IceBox ASCII files and accessing A python library and various tools for working with IceStorm ASCII files and accessing
the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file
dump of a bitstream into a Verilog file that implements an equivalent circuit. dump of a bitstream into a Verilog file that implements an equivalent circuit.
</p> </p>
@ -165,7 +181,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file.
<p> <p>
The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>. The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>.
This files contain all the relevant information for arachne-pnr to place&amp;route a design and This files contain all the relevant information for arachne-pnr to place&amp;route a design and
create an IceBox ASCII file for the placed and routed design. create an IceStorm ASCII file for the placed and routed design.
</p> </p>
<p> <p>
@ -423,7 +439,7 @@ e.g. using the following BibTeX code:
<p> <p>
<i>Documentation mostly by Clifford Wolf &lt;clifford@clifford.at&gt; in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/> <i>Documentation mostly by Clifford Wolf &lt;clifford@clifford.at&gt; in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> from Lattice and see what you can do with the information provided here.</i> Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> or <a href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">iCE40-HX8K Breakout Board</a> from Lattice and see what you can do with the tools and information provided here.</i>
</p> </p>
</body></html> </body></html>

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@ -293,7 +293,7 @@ tile are used. In IceBox nomenclature such bits are called "extra bits".
<p> <p>
The following table lists which pins / IO blocks may be used to drive The following table lists which pins / IO blocks may be used to drive
which global net, and what <span style="font-family:monospace">.extra</span> statements in the IceBox ASCII file which global net, and what <span style="font-family:monospace">.extra</span> statements in the IceStorm ASCII file
format to represent the corresponding configuration bits: format to represent the corresponding configuration bits:
</p> </p>