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<p>
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<p>
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Project IceStorm aims at reverse engineering and documenting the bitstream
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Project IceStorm aims at reverse engineering and documenting the bitstream
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format of Lattice iCE40 FPGAs and providing simple tools for analyzing and
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format of Lattice iCE40 FPGAs and providing simple tools for analyzing and
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creating bitstream files. At the moment the focus of the project is on the
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creating bitstream files. The focus of the project is on the iCE40 1K and
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HX1K-TQ144 and HX8K-CT256 devices, but most of the information is
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8K chips. (Most of the work was done on HX1K-TQ144 and HX8K-CT256 parts.)
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device-independent.
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</p>
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</p>
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<h2>Why the Lattice iCE40?</h2>
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<h2>Why the Lattice iCE40?</h2>
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@ -32,23 +31,25 @@ reverse engineering and as a reference platform for general purpose FPGA tool de
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</p>
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</p>
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<p>
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<p>
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Also, with the <a href="http://www.latticesemi.com/icestick">iCEstick</a> there is
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Also, with the <a href="http://www.latticesemi.com/icestick">Lattice iCEstick</a> there is
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a cheap and easy to use development platform available, which makes the part interesting
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a cheap and easy to use development platform available, which makes the part interesting
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for all kinds of projects.
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for all kinds of projects. (The iCEstick features an HX1K device. Lattice also sells an <a
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href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">iCE40-HX8K
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Breakout Board</a> featuring an HX8K chip.)
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</p>
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</p>
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<h2>What is the Status of the Project?</h2>
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<h2>What is the Status of the Project?</h2>
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<p>
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<p>
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We have enough bits mapped that we can create a functional Verilog model for
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We are pretty confident that we have the 1K and 8K devices completely reverse
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almost all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144
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engineered. For example, it seems we can create correct functional Verilog
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and the iCE40 HX8K-CT256, and can create bitstreams for this parts using our
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models for all bitstreams generated by Lattice iCEcube2 for the iCE40
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own tool-chain.
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HX1K-TQ144 and the iCE40 HX8K-CT256 using our <tt>icebox_vlog</tt> tool.
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</p>
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</p>
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<p>
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<p>
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The next milestones for the project are timing analysis and support for more
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Current work focuses on improvements in our timing analysis flow and support
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parts from the iCE40 family.
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for all iCE40 LP/HX 1K, 4K, and 8K devices.
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</p>
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</p>
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<h2>What is the Status of the Fully Open Source iCE40 Flow?</h2>
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<h2>What is the Status of the Fully Open Source iCE40 Flow?</h2>
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@ -66,6 +67,12 @@ arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc
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icepack rot.asc rot.bin
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icepack rot.asc rot.bin
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iceprog rot.bin</pre>
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iceprog rot.bin</pre>
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<p>
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A simple timing analysis report can be generated using the <tt>icetime</tt> utility:
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</p>
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<pre style="padding-left: 3em">icetime -tmd hx1k rot.asc</pre>
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<h2>Where are the Tools? How to install?</h2>
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<h2>Where are the Tools? How to install?</h2>
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<p>
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<p>
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@ -125,25 +132,34 @@ share regarding the install procedures on the operating system of your choice.
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<h2>What are the IceStorm Tools?</h2>
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<h2>What are the IceStorm Tools?</h2>
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<p>
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The IceStorm Tools are a couple of small programs for working with iCE40 bitstream files and our
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ASCII representation of it. The complete Open Source iCE40 Flow consists of the <a
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href="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a>, <a
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href="https://github.com/cseed/arachne-pnr">Arachne-PNR</a>, and <a
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href="http://www.clifford.at/yosys/">Yosys</a>.
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</p>
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<h3>IcePack/IceUnpack</h3>
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<h3>IcePack/IceUnpack</h3>
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<p>
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<p>
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The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceBox ASCII format
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The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceStorm ASCII format
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that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The
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that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The
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<span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file.
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<span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file. All
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other IceStorm Tools operate on the ASCII file format, not the bitstream binaries.
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</p>
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</p>
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<h3>IceTime</h3>
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<h3>IceTime</h3>
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<p>
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<p>
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The <span style="font-family:monospace">icetime</span> program is an iCE40 timing analysis tool. It reads designs in IceBox ASCII format and writes times timing
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The <span style="font-family:monospace">icetime</span> program is an iCE40 timing analysis tool. It reads designs in IceStorm ASCII format and writes times timing
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netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports.
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netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports.
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</p>
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</p>
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<h3>IceBox</h3>
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<h3>IceBox</h3>
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<p>
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<p>
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A python library and various tools for working with IceBox ASCII files and accessing
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A python library and various tools for working with IceStorm ASCII files and accessing
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the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file
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the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file
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dump of a bitstream into a Verilog file that implements an equivalent circuit.
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dump of a bitstream into a Verilog file that implements an equivalent circuit.
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</p>
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</p>
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@ -165,7 +181,7 @@ A tool for packing multiple bitstream files into one iCE40 multiboot image file.
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<p>
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<p>
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The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>.
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The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>.
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This files contain all the relevant information for arachne-pnr to place&route a design and
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This files contain all the relevant information for arachne-pnr to place&route a design and
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create an IceBox ASCII file for the placed and routed design.
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create an IceStorm ASCII file for the placed and routed design.
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</p>
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</p>
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<p>
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<p>
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@ -423,7 +439,7 @@ e.g. using the following BibTeX code:
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<p>
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<p>
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<i>Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
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<i>Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
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Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> from Lattice and see what you can do with the information provided here.</i>
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Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> or <a href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">iCE40-HX8K Breakout Board</a> from Lattice and see what you can do with the tools and information provided here.</i>
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</p>
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</p>
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</body></html>
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</body></html>
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@ -293,7 +293,7 @@ tile are used. In IceBox nomenclature such bits are called "extra bits".
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<p>
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<p>
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The following table lists which pins / IO blocks may be used to drive
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The following table lists which pins / IO blocks may be used to drive
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which global net, and what <span style="font-family:monospace">.extra</span> statements in the IceBox ASCII file
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which global net, and what <span style="font-family:monospace">.extra</span> statements in the IceStorm ASCII file
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format to represent the corresponding configuration bits:
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format to represent the corresponding configuration bits:
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</p>
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</p>
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