mirror of https://github.com/YosysHQ/icestorm.git
icepll: added -m option to choose between saving Verilog header or module
This commit is contained in:
Matthias
parent
cb38569f45
commit
14fd3eec5b
130
icepll/icepll.cc
130
icepll/icepll.cc
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@ -46,8 +46,11 @@ void help(const char *cmd)
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printf(" -S\n");
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printf(" Disable SIMPLE feedback path mode\n");
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printf("\n");
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printf(" -f <filename.v>\n");
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printf(" Save PLL configuration as Verilog module\n");
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printf(" -f <filename>\n");
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printf(" Save PLL configuration as Verilog to file\n");
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printf("\n");
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printf(" -m\n");
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printf(" Save PLL configuration as Verilog module (use with -f)\n");
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printf("\n");
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printf(" -q\n");
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printf(" Do not print PLL configuration to stdout\n");
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@ -60,11 +63,12 @@ int main(int argc, char **argv)
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double f_pllin = 12;
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double f_pllout = 60;
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bool simple_feedback = true;
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char* verilog_filename = NULL;
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char* filename = NULL;
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bool save_as_module = false;
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bool quiet = false;
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int opt;
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while ((opt = getopt(argc, argv, "i:o:S:f:q")) != -1)
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while ((opt = getopt(argc, argv, "i:o:S:mf:q")) != -1)
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{
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switch (opt)
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{
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@ -77,8 +81,11 @@ int main(int argc, char **argv)
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case 'S':
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simple_feedback = false;
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break;
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case 'm':
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save_as_module = true;
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break;
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case 'f':
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verilog_filename = optarg;
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filename = optarg;
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break;
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case 'q':
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quiet = true;
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@ -91,6 +98,10 @@ int main(int argc, char **argv)
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if (optind != argc)
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help(argv[0]);
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// error: shall save as module, but no filename was given
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if (save_as_module && filename == NULL)
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help(argv[0]);
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bool found_something = false;
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double best_fout = 0;
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int best_divr = 0;
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@ -198,53 +209,86 @@ int main(int argc, char **argv)
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printf("\n");
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}
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if (verilog_filename != NULL)
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// save PLL configuration as file
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if (filename != NULL)
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{
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// open file for writing
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FILE *f;
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f = fopen(verilog_filename, "w");
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f = fopen(filename, "w");
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// header
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fprintf(f, "/**\n * PLL configuration\n *\n"
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" * This Verilog source file was generated automatically\n"
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" * using the icepll tool from the IceStorm project.\n"
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" * Use at your own risk.\n"
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" *\n"
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" * Given input frequency: %8.3f MHz\n"
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" * Requested output frequency: %8.3f MHz\n"
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" * Achieved output frequency: %8.3f MHz\n"
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" */\n\n",
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f_pllin, f_pllout, best_fout);
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if (save_as_module)
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{
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// save PLL configuration as Verilog module
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// generate Verilog module
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fprintf(f, "module pll(\n"
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"\tinput clock_in,\n"
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"\toutput clock_out,\n"
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"\toutput locked\n"
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"\t)\n\n"
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);
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// header
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fprintf(f, "/**\n * PLL configuration\n *\n"
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" * This Verilog module was generated automatically\n"
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" * using the icepll tool from the IceStorm project.\n"
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" * Use at your own risk.\n"
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" *\n"
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" * Given input frequency: %8.3f MHz\n"
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" * Requested output frequency: %8.3f MHz\n"
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" * Achieved output frequency: %8.3f MHz\n"
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" */\n\n",
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f_pllin, f_pllout, best_fout);
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// save iCE40 PLL tile configuration
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fprintf(f, "SB_PLL40_CORE #(\n");
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fprintf(f, "\t\t.FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE"));
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fprintf(f, "\t\t.PLLOUT_SELECT(\"GENCLK\"),\n");
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fprintf(f, "\t\t.DIVR(4'b%s),\n", binstr(best_divr, 4));
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fprintf(f, "\t\t.DIVF(7'b%s),\n", binstr(best_divf, 7));
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fprintf(f, "\t\t.DIVQ(3'b%s),\n", binstr(best_divq, 3));
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fprintf(f, "\t\t.FILTER_RANGE(3'b%s),\n", binstr(filter_range, 3));
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fprintf(f, "\t) uut (\n"
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"\t\t.LOCK(locked),\n"
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"\t\t.RESETB(1'b1),\n"
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"\t\t.BYPASS(1'b0),\n"
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"\t\t.REFERENCECLK(clock_in),\n"
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"\t\t.PLLOUTCORE(clock_out),\n"
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"\t\t);\n\n"
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);
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// generate Verilog module
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fprintf(f, "module pll(\n"
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"\tinput clock_in,\n"
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"\toutput clock_out,\n"
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"\toutput locked\n"
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"\t);\n\n"
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);
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// save iCE40 PLL tile configuration
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fprintf(f, "SB_PLL40_CORE #(\n");
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fprintf(f, "\t\t.FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE"));
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fprintf(f, "\t\t.PLLOUT_SELECT(\"GENCLK\"),\n");
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fprintf(f, "\t\t.DIVR(4'b%s),\t\t" "// DIVR = %2d\n", binstr(best_divr, 4), best_divr);
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fprintf(f, "\t\t.DIVF(7'b%s),\t" "// DIVF = %2d\n", binstr(best_divf, 7), best_divf);
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fprintf(f, "\t\t.DIVQ(3'b%s),\t\t" "// DIVQ = %2d\n", binstr(best_divq, 3), best_divq);
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fprintf(f, "\t\t.FILTER_RANGE(3'b%s)\t" "// FILTER_RANGE = %d\n", binstr(filter_range, 3), filter_range);
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fprintf(f, "\t) uut (\n"
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"\t\t.LOCK(locked),\n"
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"\t\t.RESETB(1'b1),\n"
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"\t\t.BYPASS(1'b0),\n"
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"\t\t.REFERENCECLK(clock_in),\n"
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"\t\t.PLLOUTCORE(clock_out),\n"
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"\t\t);\n\n"
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);
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fprintf(f, "endmodule\n");
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}
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else
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{
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// only save PLL configuration values
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// header
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fprintf(f, "/**\n * PLL configuration\n *\n"
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" * This Verilog header file was generated automatically\n"
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" * using the icepll tool from the IceStorm project.\n"
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" * It is intended for use with FPGA primitives SB_PLL40_CORE,\n"
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" * SB_PLL40_PAD, SB_PLL40_2_PAD, SB_PLL40_2F_CORE or SB_PLL40_2F_PAD.\n"
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" * Use at your own risk.\n"
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" *\n"
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" * Given input frequency: %8.3f MHz\n"
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" * Requested output frequency: %8.3f MHz\n"
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" * Achieved output frequency: %8.3f MHz\n"
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" */\n\n",
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f_pllin, f_pllout, best_fout);
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// PLL configuration
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fprintf(f, ".FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE"));
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fprintf(f, ".PLLOUT_SELECT(\"GENCLK\"),\n");
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fprintf(f, ".DIVR(4'b%s),\t\t" "// DIVR = %2d\n", binstr(best_divr, 4), best_divr);
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fprintf(f, ".DIVF(7'b%s),\t" "// DIVF = %2d\n", binstr(best_divf, 7), best_divf);
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fprintf(f, ".DIVQ(3'b%s),\t\t" "// DIVQ = %2d\n", binstr(best_divq, 3), best_divq);
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fprintf(f, ".FILTER_RANGE(3'b%s)\t" "// FILTER_RANGE = %d\n", binstr(filter_range, 3), filter_range);
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}
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fprintf(f, "endmodule\n");
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fclose(f);
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printf("PLL configuration written to: %s\n", verilog_filename);
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printf("PLL configuration written to: %s\n", filename);
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}
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return 0;
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