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icepll: added -f option to export configuration as Verilog module

This commit is contained in:
Matthias 2017-02-01 16:54:55 +01:00
parent 29ddae9bae
commit cb38569f45
1 changed files with 58 additions and 2 deletions
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60
icepll/icepll.cc
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@ -46,8 +46,11 @@ void help(const char *cmd)
printf(" -S\n");
printf(" Disable SIMPLE feedback path mode\n");
printf("\n");
printf(" -f <filename.v>\n");
printf(" Save PLL configuration as Verilog module\n");
printf("\n");
printf(" -q\n");
printf(" Do not print PLL settings to stdout\n");
printf(" Do not print PLL configuration to stdout\n");
printf("\n");
exit(1);
}
@ -57,10 +60,11 @@ int main(int argc, char **argv)
double f_pllin = 12;
double f_pllout = 60;
bool simple_feedback = true;
char* verilog_filename = NULL;
bool quiet = false;
int opt;
while ((opt = getopt(argc, argv, "i:o:S:q")) != -1)
while ((opt = getopt(argc, argv, "i:o:S:f:q")) != -1)
{
switch (opt)
{
@ -73,6 +77,9 @@ int main(int argc, char **argv)
case 'S':
simple_feedback = false;
break;
case 'f':
verilog_filename = optarg;
break;
case 'q':
quiet = true;
break;
@ -191,5 +198,54 @@ int main(int argc, char **argv)
printf("\n");
}
if (verilog_filename != NULL)
{
// open file for writing
FILE *f;
f = fopen(verilog_filename, "w");
// header
fprintf(f, "/**\n * PLL configuration\n *\n"
" * This Verilog source file was generated automatically\n"
" * using the icepll tool from the IceStorm project.\n"
" * Use at your own risk.\n"
" *\n"
" * Given input frequency: %8.3f MHz\n"
" * Requested output frequency: %8.3f MHz\n"
" * Achieved output frequency: %8.3f MHz\n"
" */\n\n",
f_pllin, f_pllout, best_fout);
// generate Verilog module
fprintf(f, "module pll(\n"
"\tinput clock_in,\n"
"\toutput clock_out,\n"
"\toutput locked\n"
"\t)\n\n"
);
// save iCE40 PLL tile configuration
fprintf(f, "SB_PLL40_CORE #(\n");
fprintf(f, "\t\t.FEEDBACK_PATH(\"%s\"),\n", (simple_feedback ? "SIMPLE" : "NON_SIMPLE"));
fprintf(f, "\t\t.PLLOUT_SELECT(\"GENCLK\"),\n");
fprintf(f, "\t\t.DIVR(4'b%s),\n", binstr(best_divr, 4));
fprintf(f, "\t\t.DIVF(7'b%s),\n", binstr(best_divf, 7));
fprintf(f, "\t\t.DIVQ(3'b%s),\n", binstr(best_divq, 3));
fprintf(f, "\t\t.FILTER_RANGE(3'b%s),\n", binstr(filter_range, 3));
fprintf(f, "\t) uut (\n"
"\t\t.LOCK(locked),\n"
"\t\t.RESETB(1'b1),\n"
"\t\t.BYPASS(1'b0),\n"
"\t\t.REFERENCECLK(clock_in),\n"
"\t\t.PLLOUTCORE(clock_out),\n"
"\t\t);\n\n"
);
fprintf(f, "endmodule\n");
fclose(f);
printf("PLL configuration written to: %s\n", verilog_filename);
}
return 0;
}