Alan Mishchenko 677299a52f Updating print-outs.		2025-11-10 09:40:38 -08:00
..
abc	fix a bug when yosys constants are already declared	2025-06-17 16:41:43 -07:00
abci	Updating print-outs.	2025-11-10 09:40:38 -08:00
acb	Allowing the genlib reader to skip gates larger than the given size.	2024-07-10 12:59:10 -07:00
bac	Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc.	2019-03-05 15:57:50 -08:00
cba	Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers.	2021-09-26 11:30:54 -07:00
cmd	Patch to support WASI builds	2024-08-07 14:49:13 +02:00
exor	Replace `#define`s with enum constants and inline functions in `exor.h`	2024-08-02 01:07:40 +00:00
io	Fixing compiler warning.	2025-08-02 08:58:01 -07:00
main	Updating print-outs.	2025-11-10 09:40:38 -08:00
pla	Cosmetic changes after incorporating new code of 'fxch'.	2016-05-11 20:03:13 -07:00
test	Updating project settings to have simpler include paths.	2012-07-07 20:14:12 -07:00
ver	support primitive gates with names in Verilog netlist	2025-05-12 10:20:13 -04:00
wlc	Updating print-outs.	2025-11-10 09:40:38 -08:00
wln	Enabled default memory blasting when using Yosys.	2025-08-16 16:20:56 -07:00