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3249 Commits

Author SHA1 Message Date
Alan Mishchenko 677299a52f Updating print-outs. 2025-11-10 09:40:38 -08:00
Alan Mishchenko 0a650c18cf New command "&genlutcas". 2025-11-09 16:06:50 -08:00
Alan Mishchenko 6cab944535 New command %gen. 2025-11-09 11:28:25 -08:00
alanminko 3109172462
Merge pull request #443 from MyskYko/fix4 
QBF using CaDiCaL
 2025-11-06 12:46:13 -08:00
Alan Mishchenko cb971e07a3 Recent experiments. 2025-11-06 12:26:54 -08:00
Alan Mishchenko 7c6b779327 Supporting programmable cell libraries. 2025-11-01 01:23:30 -07:00
Alan Mishchenko a9d62d845d Experiments with LUT mapping. 2025-11-01 01:21:37 -07:00
Alan Mishchenko 56a7c049ae Extending max support size in "lutexact". 2025-10-30 16:35:15 -07:00
Alan Mishchenko 18f6464ec7 Experiments with LUT mapping. 2025-10-24 16:57:55 -07:00
Alan Mishchenko 3a1efd48f7 Enabling multiple LUT libraries. 2025-10-24 11:46:55 -07:00
Alan Mishchenko 4c6b082463 Reusing switch "-j" in "if" and "&if". 2025-10-24 10:59:56 -07:00
Alan Mishchenko 93f3791fbe Command "&dg" contributed by Jiun-Hao Chen from NTU. 2025-10-22 11:15:07 -07:00
Alan Mishchenko 7fbcde9d22 Correcting performance degradation introduced by a bug fix in commit e824cca0c 2025-10-10 13:47:23 -07:00
Alan Mishchenko c8eac7595d Another bug fix. 2025-10-01 22:23:27 -07:00
Alan Mishchenko 4c25599cce Exploring multiplier boundaries. 2025-09-30 15:49:14 -07:00
Alan Mishchenko 613fa4f5eb Enable saving choices in &deepsyn. 2025-09-30 15:48:45 -07:00
Alan Mishchenko 08230e0c31 Adding choice computaiton to &stochsyn. 2025-09-16 02:33:08 +07:00
Alan Mishchenko 745376d505 Reconstruction of structural choices. 2025-09-16 00:59:49 +07:00
Alan Mishchenko 9478c17288 Adding the dump of non-decomposable functions in "lutcasdec". 2025-08-31 20:18:30 -07:00
jiunhaochen 4f29be9046 rewire support timing-constraint 2025-08-27 00:56:43 +08:00
Alan Mishchenko 192c161f93 Enabled default memory blasting when using Yosys. 2025-08-16 16:20:56 -07:00
Alan Mishchenko c5ceff2bee Dumping a binary file with truth tables in "if". 2025-08-12 16:00:26 -07:00
Alan Mishchenko e29dcd9f32 Adding a way to dump sets of resub problems. 2025-08-11 22:44:46 -07:00
Alan Mishchenko e7d360811f Fixed combo loop in choice computation. 2025-08-10 11:04:20 -07:00
Alan Mishchenko 15151c58ed Updating &stochsyn with switch '-d' to support level-preserving AIG optimizations. 2025-08-09 18:10:32 -07:00
Alan Mishchenko 00910e36ff Fixing typos. 2025-08-09 17:00:02 -07:00
Alan Mishchenko a5715bc32d Updates to the prefix tree generation. 2025-08-09 16:43:55 -07:00
Alan Mishchenko 5e09cca964 Handing the case of signed comparators. 2025-08-09 14:46:45 -07:00
Alan Mishchenko 1a18c9a3d8 : lutexact 2025-08-07 12:35:03 -07:00
Alan Mishchenko fd74cb8e8a Refactored the code to return prefix tree as an array of GP-nodes. 2025-08-07 10:51:05 -07:00
Alan Mishchenko 260fa85161 Fixing a linker problem. 2025-08-06 07:38:27 -07:00
Alan Mishchenko c738ed6e86 Integrating prefix adder generation code by Martin Povišer 2025-08-05 22:50:06 -07:00
Alan Mishchenko 0218e3e4cb New command for bound-set evaluation. 2025-08-03 20:10:26 -07:00
Alan Mishchenko aeef2c6692 Fixing compiler warning. 2025-08-02 08:58:01 -07:00
Alan Mishchenko 3aa8a4a639 New command to dump circuit structure into a file. 2025-08-02 08:53:22 -07:00
Alan Mishchenko c69e45916a Update &append to share primary inputs. 2025-08-01 14:29:45 -07:00
Alan Mishchenko 052a365823 Undoing previous commit. 2025-07-28 22:58:24 -07:00
Alan Mishchenko 705a3da338 Saving box info for XAIG created usign %blast. 2025-07-28 22:52:27 -07:00
Alan Mishchenko 4ccacb1e5b Adding printout of don't-cares after mapping. 2025-07-21 10:22:43 -07:00
Alan Mishchenko ff56eed4b3 Allowing "lutexact" to take truth table from the current network. 2025-07-21 07:56:30 -07:00
Alan Mishchenko a511d753a6 Improvements to "lutcasdec". 2025-07-20 18:29:20 -07:00
Alan Mishchenko d0118d3917 Adding JSONC parser. 2025-07-14 10:34:24 -07:00
Alan Mishchenko f1eebf78f4 Updating command "runscript". 2025-07-08 19:06:04 -07:00
MyskYko 13205ccbb3 qbf with cadical 2025-06-21 01:29:26 -07:00
MyskYko e9845e534a fix a bug when yosys constants are already declared 2025-06-17 16:41:43 -07:00
alanminko 5cf5a8d9f5
Merge pull request #412 from tklam/feature/support_verilog_gate_name 
Support primitive gates with names in Verilog netlist
 2025-06-07 10:38:03 -07:00
Alan Mishchenko 1f98c28011 Improved cascade printout in "lutcasdec". 2025-05-25 22:24:33 -07:00
Alan Mishchenko 301b46e3c1 Fixiing BLIF reader to read Yosys constants. 2025-05-25 18:45:59 -07:00
Alan Mishchenko 0ae04514cd Work-around for a bug in "lutcasdec". 2025-05-22 23:56:40 -07:00
Alan Mishchenko 716314d835 Generating AIGs for adders. 2025-05-22 23:56:13 -07:00