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mirror of https://github.com/YosysHQ/abc.git synced 2026-09-01 02:08:10 +02:00
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573d6d7ab7b24739b22ba1a2876b076c0ee09e40
abc/src/map
T
History
Alan Mishchenko 573d6d7ab7 Enable wire load estimation in buffering/sizing.
2013-08-10 10:27:55 -07:00
..
amap
Adding a wrapper around clock() for more accurate time counting in ABC.
2013-05-27 15:09:23 -07:00
cov
Adding a wrapper around clock() for more accurate time counting in ABC.
2013-05-27 15:09:23 -07:00
fpga
Updating project settings to have simpler include paths.
2012-07-07 20:14:12 -07:00
if
Temprary changes.
2013-07-18 15:40:45 -07:00
mapper
Parametrizing standard-cell mapper to account for the fanout delay.
2013-07-30 00:18:57 -07:00
mio
Improved gate-sizing.
2013-07-29 10:10:21 -07:00
mpm
Restructuring gate-sizing code trying to separate timing analysis.
2013-07-21 17:55:15 -07:00
scl
Enable wire load estimation in buffering/sizing.
2013-08-10 10:27:55 -07:00
super
Adding a wrapper around clock() for more accurate time counting in ABC.
2013-05-27 15:09:23 -07:00
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