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mirror of https://github.com/YosysHQ/abc.git synced 2026-09-01 02:08:10 +02:00
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14a1ea844764de72a3935bc49f55d6170958aa27
abc/src/aig
T
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Alan Mishchenko 14a1ea8447 Adding switch &st -s for MUX restructring.
2019-04-21 17:15:08 -07:00
..
aig
Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc.
2019-03-05 15:57:50 -08:00
gia
Adding switch &st -s for MUX restructring.
2019-04-21 17:15:08 -07:00
hop
Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes.
2017-12-03 14:39:11 -08:00
ioa
Bug fixes in the above patches.
2013-12-03 00:38:37 -08:00
ivy
Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc.
2019-03-05 15:57:50 -08:00
miniaig
Supporting LUT in NDR and WLC.
2019-04-05 21:08:46 -10:00
saig
Adding switch 'scorr -f' to dump inductive invariant as an AIG.
2018-03-22 10:10:09 -07:00
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