 Alan Mishchenko
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f91f23bed0
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Adding new switch 'bdd -s' to translate SOP directly into BDD.
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2016-04-24 00:13:07 +03:00 |
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Alan Mishchenko
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67bfb4ba09
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Improved algo for edge computation.
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2016-04-23 15:13:22 +03:00 |
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Alan Mishchenko
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1b550cb87b
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Improved algo for edge computation.
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2016-04-22 08:36:05 +03:00 |
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Alan Mishchenko
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813b0e5851
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Experimental algorithm for edge optimization.
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2016-04-13 15:54:14 -07:00 |
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Alan Mishchenko
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b9e403b46e
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Bug fix: change in the ordering of the reset flop (should be last, not first).
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2016-04-13 09:14:54 -07:00 |
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Alan Mishchenko
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847ac96f6e
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Updates to Exorcism package
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2016-04-11 22:55:06 -07:00 |
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Alan Mishchenko
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9522aeea19
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Updates to Exorcism package
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2016-04-11 22:29:37 -07:00 |
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Alan Mishchenko
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a02be725e9
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Updates to Exorcism package
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2016-04-11 21:48:54 -07:00 |
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Alan Mishchenko
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2d6a6f6654
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Added Exorcism package, reading ESOP (read_pla -x file.esop) and deriving AIG (cubes -x; st).
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2016-04-11 21:42:00 -07:00 |
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Alan Mishchenko
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2d1d315ece
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Supporting edge information during mapping.
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2016-04-11 18:41:18 -07:00 |
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Alan Mishchenko
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d0a0cf6395
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Command &esop to convert AIG into ESOP.
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2016-04-09 17:00:46 -07:00 |
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Alan Mishchenko
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3b694a7089
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Adding AIG rehashing after LUT mapping in Gia.
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2016-04-07 20:03:31 -07:00 |
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Alan Mishchenko
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26ec3868f6
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Adding AIG rehashing after LUT mapping in Gia.
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2016-04-07 19:16:51 -07:00 |
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Alan Mishchenko
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887f3c21cc
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Supporting edges in delay-optimization in &satlut.
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2016-04-07 17:15:24 -07:00 |
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Alan Mishchenko
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f05986f7b3
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Supporting edges in delay-optimization in &satlut.
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2016-04-07 15:54:50 -07:00 |
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Alan Mishchenko
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95ab749087
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Supporting edges in delay-optimization in &satlut.
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2016-04-07 13:20:41 -07:00 |
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Alan Mishchenko
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b31b6fec77
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Supporting edge information during mapping.
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2016-04-06 15:43:03 -07:00 |
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Alan Mishchenko
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ee17cbbf4b
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Supporting negative and reverse ranges of word-level variables in Wlc.
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2016-04-04 18:09:41 -07:00 |
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Alan Mishchenko
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ac7a799076
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Improvements to delay-optimization in &satlut.
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2016-04-04 14:27:14 -07:00 |
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Alan Mishchenko
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720082753f
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Improvements to delay-optimization in &satlut.
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2016-04-04 12:51:05 -07:00 |
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Alan Mishchenko
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4a954c1b23
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Improvements to delay-optimization in &satlut.
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2016-04-04 08:43:22 -07:00 |
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Alan Mishchenko
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e0ad9de7ea
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Improvements to delay-optimization in &satlut.
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2016-04-03 16:44:13 -07:00 |
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Alan Mishchenko
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d53161a7e1
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Enabling native Gia visualization in &show.
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2016-04-03 15:42:08 -07:00 |
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Alan Mishchenko
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9074d19d69
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Allowing Cba manager to be derived from another Cba manager.
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2016-04-02 16:04:15 -07:00 |
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Alan Mishchenko
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7724dfcca2
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Windowing for technology mapping.
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2016-03-30 21:51:50 -07:00 |
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Alan Mishchenko
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e026f05ae3
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Bug fix in truth table reading for funcs with less than 6 vars.
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2016-03-28 10:18:17 -07:00 |
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Alan Mishchenko
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72ffddb0ad
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Sorting multiplier inputs based on the number of constant bits.
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2016-03-24 17:45:51 -07:00 |
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Alan Mishchenko
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a4d6e2f8c9
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Typo in operator in Wlc_Ntk_t.
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2016-03-18 20:47:21 -07:00 |
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Alan Mishchenko
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65ee47c515
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Supporting bit-wise XNOR operator in Wlc_Ntk_t.
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2016-03-18 13:58:22 +08:00 |
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Alan Mishchenko
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b2ad140adb
|
Supporting complemented reduction operators.
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2016-03-11 15:12:52 +09:00 |
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Alan Mishchenko
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74328f52da
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Supporting complemented reduction operators.
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2016-03-10 23:03:53 +09:00 |
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Alan Mishchenko
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847d661bee
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Change error to warning in 'scorr'.
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2016-03-09 09:33:10 +09:00 |
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Alan Mishchenko
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12fac91fba
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Supporting ~^ as equality operator in Wlc.
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2016-03-04 09:17:39 +09:00 |
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Alan Mishchenko
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cf702af6f1
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New hierarchical TT NPN matching.
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2016-02-26 18:20:57 +08:00 |
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Alan Mishchenko
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c8962e94e2
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Improving bit-blasting of a multiplier and squarer.
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2016-02-13 18:51:42 -08:00 |
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Alan Mishchenko
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390a145f0a
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Adding support for a different bit-blasting of a multiplier and squarer.
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2016-02-13 15:15:01 -08:00 |
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Alan Mishchenko
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e0616441b3
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Adding support for a different bit-blasting of a multiplier and squarer.
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2016-02-12 09:46:49 -08:00 |
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Alan Mishchenko
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66796c3808
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Experiments with SAT-based mapping.
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2016-02-08 16:29:36 -08:00 |
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Alan Mishchenko
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0224039132
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Added recursive bit-blasting of a carry-lookahead adder.
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2016-02-06 12:08:23 -08:00 |
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Alan Mishchenko
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be35a13a4c
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Preserving internal signal names when 'strash' is not used.
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2016-02-03 13:56:27 -08:00 |
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Alan Mishchenko
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8bcf8fd3c9
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Supporting X-valued constants in Wlc_Ntk_t.
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2016-02-02 16:40:29 -08:00 |
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Alan Mishchenko
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094c68f921
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Supporting X-valued constants in Wlc_Ntk_t.
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2016-02-02 16:20:19 -08:00 |
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Alan Mishchenko
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c81b6cb515
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Supporting X-valued constants in Wlc_Ntk_t.
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2016-02-02 15:43:19 -08:00 |
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Alan Mishchenko
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02725c9eca
|
An add-on to write Verilog for circuits mapped into simple gates.
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2016-02-01 15:56:53 -08:00 |
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Alan Mishchenko
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9ef447658e
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Bug fix in 'aig', for the case of non-min-base SOPs.
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2016-01-20 15:01:53 -08:00 |
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Alan Mishchenko
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df34a26216
|
Generating sorting network as a PLA file.
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2016-01-20 15:01:27 -08:00 |
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Alan Mishchenko
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f5ee46eb3c
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New command to dump LUT network.
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2016-01-16 17:35:46 -08:00 |
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Alan Mishchenko
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c4446189a9
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Changes to PDR to compute f-inf clauses and import invariant (or clauses) as a network.
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2016-01-14 20:42:22 -08:00 |
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Alan Mishchenko
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87f6828d50
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Adding support for delay/area tradeoff.
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2016-01-13 12:13:54 -08:00 |
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Alan Mishchenko
|
8dd31fb4a9
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Integrating new CNF generation into &bmc.
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2016-01-12 22:07:01 -08:00 |
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