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3,406 Commits 27 Branches 57 Tags 58 MiB
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23 Commits

Author SHA1 Message Date
Alan Mishchenko e0616441b3 Adding support for a different bit-blasting of a multiplier and squarer. 2016-02-12 09:46:49 -08:00
Alan Mishchenko 8bcf8fd3c9 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 16:40:29 -08:00
Alan Mishchenko 094c68f921 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 16:20:19 -08:00
Alan Mishchenko c81b6cb515 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 15:43:19 -08:00
Alan Mishchenko e37bd1fb64 Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator (@). 2015-07-14 19:55:05 -07:00
Alan Mishchenko 6bd77858c5 Bug fixing in %blast when blasting MUX coming from always-statement. 2015-07-07 22:34:21 -07:00
Alan Mishchenko 8efc9cb7a9 Bug fixing in %blast when blasting mod operator (handling zero divisor). 2015-07-07 15:38:54 -07:00
Alan Mishchenko 360cc99f01 Bug fix WLC package (reusing name buffer, resulting in wrong print-outs). 2015-03-03 12:52:47 -08:00
Alan Mishchenko 8ff4b79fc2 Several ongoing changes. 2015-01-26 20:48:59 -08:00
Alan Mishchenko 65cd556b1d Outputting initial state in Wlc_Ntk_t. 2015-01-26 09:14:51 -08:00
Alan Mishchenko 416cc3b2ae Outputting initial state in Wlc_Ntk_t. 2015-01-25 11:21:36 -08:00
Alan Mishchenko 98c5668d4b Improvements to word-level network package. 2014-11-14 20:15:36 -08:00
Alan Mishchenko cc37fb9573 Improvements to word-level network package. 2014-11-14 20:12:20 -08:00
Alan Mishchenko 3f31a8580f Bug fix in Verilog writer. 2014-10-02 14:53:30 -07:00
Alan Mishchenko 6d94b6b1a2 Improvements to bit-blaster. 2014-10-01 22:54:08 -07:00
Alan Mishchenko fbc9c00fd1 Renaming DSD commands (dsd_tune -> dsd_match; dsd_clean -> dsd_filter). 2014-09-28 11:32:26 -07:00
Alan Mishchenko 69bd355467 Support for sequential designs in word-level Verilog. 2014-09-26 16:11:36 -07:00
Alan Mishchenko a4d5a9b5bc Added support of word-level MUXes represented as 'always'-statements. 2014-09-24 00:22:18 -04:00
Alan Mishchenko 69827a5a88 Improvements to word-level Verilog parser. 2014-09-17 15:20:04 -07:00
Alan Mishchenko ffd77ffedd Improvements to word-level Verilog parser. 2014-09-17 15:14:17 -07:00
Alan Mishchenko ec0b9b6b6e Improvements to word-level Verilog parser. 2014-09-16 22:08:22 -07:00
Alan Mishchenko 501c3f0b1e Compiler warnings. 2014-09-12 13:53:04 -07:00
Alan Mishchenko dcb7d0d3fc New word-level representation package. 2014-09-12 13:40:48 -07:00