mirror of https://github.com/YosysHQ/abc.git
Improvements to word-level Verilog parser.
This commit is contained in:
parent
ffd77ffedd
commit
69827a5a88
|
|
@ -705,8 +705,9 @@ int Wlc_PrsDerive( Wlc_Prs_t * p )
|
|||
if ( Wlc_PrsStrCmp( pName, "table" ) )
|
||||
{
|
||||
// THIS IS A HACK TO DETECT tables
|
||||
int Width1, Width2;
|
||||
int v, b, Value, nBits, nInts, * pTable;
|
||||
int Width1 = -1, Width2 = -1;
|
||||
int v, b, Value, nBits, nInts;
|
||||
unsigned * pTable;
|
||||
Vec_Int_t * vValues = Vec_IntAlloc( 256 );
|
||||
Wlc_PrsForEachLineStart( p, pStart, i, i+1 )
|
||||
{
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ void Wlc_WriteTableOne( FILE * pFile, int nFans, int nOuts, word * pTable, int I
|
|||
fprintf( pFile, " begin\n" );
|
||||
fprintf( pFile, " case (ind)\n" );
|
||||
for ( m = 0; m < nMints; m++ )
|
||||
fprintf( pFile, " %d\'h%x: val = %d\'h%x;\n", nFans, m, nOuts, (pTable[(nOuts * m) >> 6] >> ((nOuts * m) & 63)) & Abc_Tt6Mask(nOuts) );
|
||||
fprintf( pFile, " %d\'h%x: val = %d\'h%x;\n", nFans, m, nOuts, (unsigned)((pTable[(nOuts * m) >> 6] >> ((nOuts * m) & 63)) & Abc_Tt6Mask(nOuts)) );
|
||||
fprintf( pFile, " endcase\n" );
|
||||
fprintf( pFile, " end\n" );
|
||||
fprintf( pFile, "endmodule\n" );
|
||||
|
|
|
|||
Loading…
Reference in New Issue