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Author SHA1 Message Date
Matt Liberty 66f5d7c7a2 mainUtils: match readline behavior when ABC_USE_READLINE is undefined 
The non-readline branch of Abc_UtilsGetUsersInput has three behavioral
gaps versus the readline branch that break callers driving abc as a
coprocess over a pipe (e.g. yosys's passes/techmap/abc.cc, which spawns
"abc -s" with piped stdin/stdout and uses read_until_abc_done to wait
for "abc NN> <command>" lines):

  1. The prompt is written with fprintf() and never flushed. On a pipe
     stdout is fully buffered, so the prompt never reaches the reader.
     The reader waits for the prompt, abc waits in fgets(), deadlock.

  2. There is no echo of the line read from stdin. readline() emits
     each character to its output stream; yosys's protocol depends on
     seeing "abc NN> source ...\n" in the output to advance state.
     Without an echo it waits forever.

  3. EOF on stdin is silently ignored: fgets() returns NULL but the
     function returns a stale Prompt buffer, causing a tight loop on
     pipe close. The readline branch exit(0)s on NULL.

Fix all three. Echo only when stdin is not a tty -- on a tty the kernel
already echoes typed characters during cooked input, so double-echo
would be visible to interactive users.

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
 2026-06-05 06:05:32 +00:00
Alan Mishchenko 21b2d8959a Add output name permutation in &cec. 2026-06-04 21:05:04 +07:00
alanminko a917c1af9f
Merge pull request #509 from fxreichl/master 
Add option for lut optimisation
 2026-05-21 23:44:41 -07:00
Alan Mishchenko cd6e9b582b Modify default intermediate AIGER file name. 2026-05-21 23:41:12 -07:00
Franz Reichl 70c42b7292 Add option for lut optimisation 2026-05-21 11:58:13 +02:00
Alan Mishchenko f4d870e109 Updating interface of "twoexaxct". 2026-05-18 07:31:39 -07:00
Alan Mishchenko ffb0ff63fc Updating interface of %yosys to take multiple Verilog files. 2026-05-18 07:23:18 -07:00
Alan Mishchenko 07e38ef030 Imrpovements in "twoexact". 2026-05-17 18:51:49 -07:00
Alan Mishchenko 7bf1177d39 Add MM-based adder generation to &genadder. 2026-05-15 17:57:45 -07:00
Alan Mishchenko 26567123a7 Fix warnings. 2026-05-15 17:47:46 -07:00
alanminko 2827348459
Merge pull request #507 from Meneya/bmc3c 
Added option -c to call CaDiCaL solver inside bmc3 engine (bmc3 -c)
 2026-05-15 07:54:43 -07:00
Alan Mishchenko c61f1a04e9 Bug fix in handling ufar calls. 2026-05-11 19:27:06 -07:00
xiran d55ae1421c New feature: Add incremental refinement to &scorr command 2026-05-10 22:58:10 -07:00
Alan Mishchenko d54cbda229 Multi-output gate mapper. 2026-05-10 09:52:16 -07:00
Alan Mishchenko f3157272ae Initial support of multi-output gates in sizing. 2026-05-08 16:03:24 -07:00
Alan Mishchenko eaa8496b42 Streamlining support for multi-output gates 2026-05-08 00:45:46 -07:00
Alan Mishchenko fc4cfc0c35 Extending support for sequential AIGs. 2026-05-04 18:56:14 -07:00
alanminko ec4faae74a
Merge pull request #501 from petterreinholdtsen/writepla-assert-relaxed 
Relaxed assert in Io_WritePla() to avoid failure with too shallow network.
 2026-05-02 21:16:35 -07:00
Alan Mishchenko ff00f67063 Updating verilog writer. 2026-05-02 08:22:59 -07:00
Alan Mishchenko c20832627f Extending &sprove interface 2026-04-25 17:45:55 -07:00
Petter Reinholdtsen 2b9920e6a5 Relaxed assert in Io_WritePla() to avoid failure with too shallow network. 
Otherwise the abc will refuse to output trivial functions(constant 1 or 0).

The issue was originally submitted to
<URL: https://bitbucket.org/alanmi/abc/issue/27/assertion-failure-in-write_pla-command >,
now available via
<URL: https://web.archive.org/web/20200621081236/https://bitbucket.org/alanmi/abc/issues/27/assertion-failure-in-write_pla-command >.
Sadly the example demonstrated the problem was not archived.

This issue was also reported as <URL: https://bugs.debian.org/780450 >.
 2026-04-23 12:55:49 +02:00
Meneya 5096a78fbe Added option -c to call CaDiCaL solver inside bmc3 engine (bmc3 -c) 2026-04-20 14:53:32 +05:30
Franz Reichl 0f6ca59029 Extend the eSLIM package 2026-04-14 15:33:57 +02:00
Alan Mishchenko 8aa7e12dab Adding trace logging to &sprove. 2026-04-11 21:14:19 -07:00
Alan Mishchenko 80c8a9a192 Bug fix in %blast. 2026-04-06 20:42:44 -07:00
Alan Mishchenko cd2998b5c7 Adding name-based input reordering in &cec. 2026-04-03 21:18:41 -07:00
Alan Mishchenko bef23270f8 Improvements to command "history". 2026-03-27 20:09:54 -07:00
Alan Mishchenko b8059c310a Add support for second Verilog files in %ysoys and &cec 2026-03-27 19:24:31 -07:00
Alan Mishchenko ceebb2d167 Updated to &sprove. 2026-03-23 14:55:27 -07:00
Alan Mishchenko fa5029da95 Updates to &if mapper. 2026-03-10 22:19:37 -07:00
Alan Mishchenko 7ae0f4966a Adding gla to sprove. 2026-03-08 12:04:38 -07:00
Alan Mishchenko ba69519d73 Adding command for calling external solvers. 2026-03-08 10:26:27 -07:00
Alan Mishchenko ef54c1daea Updating interface of &cec. 2026-02-24 14:59:13 -08:00
Alan Mishchenko c7ea67b7df Update command "history". 2026-02-18 12:19:32 -08:00
Alan Mishchenko 3dd086febe New command &divide, etc. 2026-02-18 10:02:42 -08:00
Alan Mishchenko 3cdb1c4c3b Dumping LUT-mapped networks in Vivado-readable Verilog. 2026-02-15 19:26:35 -08:00
Alan Mishchenko 8475386dfa Making %ufar preserve AIG name. 2026-02-13 09:52:37 -08:00
Alan Mishchenko 2726f0e470 Fixing compiler problem. 2026-02-13 07:12:50 -08:00
Alan Mishchenko 3285adaf32 Updating &sprove to run %ufar. 2026-02-13 07:04:50 -08:00
Alan Mishchenko 90be4816ce Updating delay trace for LUT mapping. 2026-02-08 22:50:12 -08:00
Alan Mishchenko 8573cb98f6 Bug fix in %blast. 2026-02-03 11:52:21 -08:00
Alan Mishchenko ccafa23e40 Extending &funtrace. 2026-02-03 11:17:26 -08:00
Alan Mishchenko 367b407fba Extending "lutexact" to get function from the current network. 2026-02-01 19:47:14 -08:00
alanminko 70a12750c1
Merge pull request #475 from wjrforcyber/master 
Fix(&put): Missing spec in cec
 2026-02-01 07:55:20 -08:00
alanminko 5fd7c57407
Merge pull request #477 from YosysHQ/wasi_upstream 
MINGW and WASI compile fixes (from YosysHQ fork)
 2026-02-01 07:55:05 -08:00
Miodrag Milanovic f2ae808236 MINGW proper pthread handling 2026-01-29 09:28:21 +01:00
Alan Mishchenko 29656286cf New command &init1. 2026-01-28 18:39:21 +07:00
Alan Mishchenko 71e163571a Rename ID mapping switch in &verify. 2026-01-27 22:03:41 +07:00
JingrenWang 5f3a4fec83
Fix(&put): Missing spec in cec 
Signed-off-by: JingrenWang <wjrforcyber@163.com>
 2026-01-23 07:05:10 +08:00
Alan Mishchenko cdcfb2febf Changing some default return values to make sure scripts do not abort. 2026-01-21 08:18:01 +07:00