Commit Graph

16 Commits

Author SHA1 Message Date
Alan Mishchenko a2d97cf2b6 Debugging and finetuning the flow. 2013-09-17 16:43:42 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko ff5d3591d1 Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:23:49 -07:00
Alan Mishchenko ae27704c13 Integrated buffering and sizing. 2013-08-11 11:35:22 -07:00
Alan Mishchenko 6c4252c5c9 Integrated buffering and sizing. 2013-08-10 18:11:09 -07:00
Alan Mishchenko 573d6d7ab7 Enable wire load estimation in buffering/sizing. 2013-08-10 10:27:55 -07:00
Alan Mishchenko 4af5587cbf Integrated buffering and sizing. 2013-08-09 21:44:18 -07:00
Alan Mishchenko 633db0f4ad Improvements to buffering and sizing. 2013-08-09 17:54:18 -07:00
Alan Mishchenko 95684b044a Improvements to buffering and sizing. 2013-08-09 11:15:20 -07:00
Alan Mishchenko 881b2ec46f Integrated buffering and sizing. 2013-08-08 18:23:00 -07:00
Alan Mishchenko 8576e4b440 Improvements to buffering and sizing. 2013-08-06 22:51:39 -07:00
Alan Mishchenko 1558fe6110 Adding code to estimate buffer trees. 2013-08-05 10:45:06 -07:00
Alan Mishchenko 1dca7458f3 Improved buffering. 2013-07-29 18:55:13 -07:00
Alan Mishchenko 84c0b9d69b Tuning standard-cell mapping flow. 2013-07-23 16:15:03 -07:00
Alan Mishchenko f392645daf Generating GENLIB library from SCL. 2013-07-22 13:25:51 -07:00
Alan Mishchenko fd28deefc7 Restructuring gate-sizing code trying to separate timing analysis. 2013-07-21 17:55:15 -07:00