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1,163 Commits 27 Branches 57 Tags 58 MiB
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477 Commits

Author SHA1 Message Date
Alan Mishchenko e8d690f2a4 Adding command 'testdec'. 2012-07-28 18:30:21 -07:00
Alan Mishchenko 1e159a826e Started implementing command 'testdec'. 2012-07-28 12:42:17 -07:00
Alan Mishchenko b2ad079a2a Allow for skipping structural hashing when reading GIA from file. 2012-07-25 12:37:19 -07:00
Alan Mishchenko 7dc8c81ff6 Allow for skipping structural hashing when reading GIA from file. 2012-07-25 08:59:24 -07:00
Alan Mishchenko f09afdf24c Added switch &trim -c to additionally remove direct connections (POs fed by PIs). 2012-07-20 13:52:39 -07:00
Alan Mishchenko aa78ce56e7 Updated code for lazy man's synthesis. 2012-07-20 11:52:51 -07:00
Alan Mishchenko 2279a538b7 New procedures to generate NPN-classes for a library of 6-input functions. 2012-07-19 20:38:03 -07:00
Alan Mishchenko 1fe2ba9ac0 Enabling &gla for combinational miters. 2012-07-18 23:52:41 -07:00
Alan Mishchenko 96d7699698 Updated code for lazy man's synthesis. 2012-07-15 15:54:36 -07:00
Alan Mishchenko d3ad7fbaf3 Several small changes and fixes. 2012-07-13 15:02:46 -07:00
Alan Mishchenko b9ee5d8564 Improvements in the proof-logging SAT solver. 2012-07-11 12:45:46 -07:00
Alan Mishchenko 637736827a Adding several command-line arguments to 'dsat'. 2012-07-09 19:24:39 -07:00
Alan Mishchenko 685faae8e2 Added command &gla_purify. 2012-07-08 17:56:49 -07:00
Alan Mishchenko 6c3363f777 Adding restart to rarity simulation in sim3 and &sim3. 2012-07-08 13:23:05 -07:00
Alan Mishchenko 1c33107cbb Updating project settings to have simpler include paths. 2012-07-07 20:14:12 -07:00
Alan Mishchenko 3aab724573 Fixing time primtouts throughout the code. 2012-07-07 17:46:54 -07:00
Alan Mishchenko 5fb7c676c2 Procedure to compute truth tables for POs of GIA. 2012-07-07 13:13:32 -07:00
Alan Mishchenko 5008b1a4f3 Commands &fla_gla/&gla_fla to convert between flop-level and gate-level abstraction. 2012-07-06 20:41:11 -07:00
Alan Mishchenko e879f0f6d1 Tentatively retiring command &abs_start, &abs_cba, &abs_pba, &gla_cba, &gla_pba. 2012-07-06 18:50:50 -07:00
Alan Mishchenko 23467b83b6 Setting infinite default conflict limits in 'bmc', 'int', 'pdr'. 2012-07-06 18:48:35 -07:00
Alan Mishchenko 8b0302cdab Changing default conflict limits in bmc2 and bmc3 to be 0 (no limit). 2012-07-05 13:32:52 -07:00
Alan Mishchenko 3c43fbba1a Other improvements to &vta and &gla. 2012-07-05 13:09:41 -07:00
Alan Mishchenko ce6e6551c3 Other improvements to &vta and &gla. 2012-07-04 18:23:33 -07:00
Alan Mishchenko d3c018cd23 Reducing memory usage in bmc2 and bmc3. 2012-07-01 02:19:19 -07:00
Alan Mishchenko a4908534f1 Bug fix in &vta. 2012-06-29 15:17:03 -07:00
Alan Mishchenko 051cc64ee2 Gate level abstraction (command &gla). 2012-06-28 23:06:07 -07:00
Alan Mishchenko 520c436d28 Gate level abstraction (command &gla). 2012-06-28 16:44:03 -07:00
Alan Mishchenko 7629fd6aea Added min-cut-based refinement of gate-level abstraction (command &gla_refine). 2012-06-24 18:45:42 -07:00
Alan Mishchenko 3c0a9e0862 Switch -A <file_name> to specify file name for dumping abstrated model with &vta -d. 2012-06-21 20:20:26 -07:00
Alan Mishchenko c6af9094c0 Changing 'if' to allow for delay optimization on sequential paths only. 2012-05-20 17:27:53 +07:00
Alan Mishchenko 76539c1956 Added generation of multipliers in 'gen'. 2012-05-15 09:34:24 +07:00
Alan Mishchenko aa087d2513 Making sure cec -n and dsec -n do not remove the I/O names in the current network. 2012-05-08 13:37:19 +08:00
Alan Mishchenko 2c6faa0607 Compilation problem caused by multiple declarations. 2012-04-28 16:04:17 +07:00
Alan Mishchenko 78855cc952 Added supporting dual-output seq miters in &trim. 2012-04-28 04:19:26 +07:00
Alan Mishchenko 2bf7454b41 Added supporting dual-output seq miters in &iso. 2012-04-28 02:21:06 +07:00
Alan Mishchenko 590202e327 Set the failed output index if ORing of outputs was done in 'int'. 2012-04-27 16:14:40 +07:00
Alan Mishchenko 92ad58ffa2 Adding iterative refinement to 'addbuffs'. 2012-04-13 18:20:44 -07:00
Alan Mishchenko 7e21f01269 Updated used message for 'back_reach'. 2012-04-13 15:41:31 -07:00
Alan Mishchenko 0184dab4de Adding iterative refinement to 'addbuffs'. 2012-04-11 16:00:09 -07:00
Alan Mishchenko 0d802453e4 Adding reverse order to 'addbuffs'. 2012-04-11 08:09:31 -07:00
Alan Mishchenko 0509440a45 Improving printouts of critical path. 2012-04-09 15:06:33 -07:00
Alan Mishchenko 48b47300e3 Added dumping abstracted model in &vta. 2012-04-07 12:43:17 -07:00
Alan Mishchenko a21f2986aa Enabling mapping into multi-input AND/OR gates. 2012-03-27 20:15:02 -07:00
Alan Mishchenko 8ed3e40a52 Logic sharing for multi-input gates. 2012-03-25 22:47:08 -07:00
Alan Mishchenko b4df114e4a Logic sharing for multi-input gates. 2012-03-25 16:49:29 -07:00
Alan Mishchenko 309bcf2dec Logic sharing for multi-input gates. 2012-03-25 01:24:26 -07:00
Alan Mishchenko abb889fe6e Improving printouts of gates and support. 2012-03-24 13:15:37 -07:00
Alan Mishchenko 3abd9773a4 Enabled demitering dual-output miters. 2012-03-23 22:52:30 -07:00
Alan Mishchenko 1c31dbe786 Added command 'addbuffs' to create balanced CI/CO paths. 2012-03-23 22:29:25 -07:00
Alan Mishchenko 0792ab0eb6 Additional features for delay optimization 2012-03-21 23:19:49 -07:00