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1590 Commits

Author SHA1 Message Date
Alan Mishchenko 867600b766 Supporting the decoder primitive in NDR and bit-blasting. 2018-06-05 16:23:04 -07:00
Alan Mishchenko 044c7a0794 Disabling unused feature in &nf. 2018-06-04 11:01:39 -07:00
Alan Mishchenko 21c7dad7e4 Supporting NMUX and SEL in NDR. 2018-05-24 19:36:28 +09:00
Alan Mishchenko aa313189c4 Updates to NDR format (bug fixes). 2018-05-03 22:28:21 -07:00
Alan Mishchenko f23ea8e33f Updates to NDR format (flops, memories, signed mult, etc). 2018-04-29 15:14:01 -07:00
Alan Mishchenko fa00219d4c Adding switch &w -p to dump AIG in a Verilog file. 2018-04-25 16:58:29 -07:00
Alan Mishchenko 37504a492a Adding adder-subtractor primitive. 2018-04-11 19:08:53 -07:00
Alan Mishchenko a8f913f75a Making sure duplicated inverters are not created. 2018-04-11 18:33:00 -07:00
Alan Mishchenko a2d59be3f7 Integrating SAT-based CEX minimization (bug fix). 2018-03-25 18:19:06 -07:00
Alan Mishchenko e639e8fd1b Integrating SAT-based CEX minimization. 2018-03-25 16:46:09 -07:00
Alan Mishchenko a6d489e7d8 Updating &mfs to support hard objects. 2018-03-23 21:32:14 -07:00
Alan Mishchenko 53e7d1f9ef Adding switch 'scorr -f' to dump inductive invariant as an AIG. 2018-03-22 10:10:09 -07:00
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko 33971604cf Adding support for adders with carry-in in WLC and NDR. 2018-02-24 09:50:24 -08:00
Alan Mishchenko b2055bd637 Improvements to circuit based solver. 2018-02-20 16:00:58 -08:00
Alan Mishchenko 1d1b11cb65 Improvements to circuit based solver. 2018-02-17 13:10:48 -08:00
Alan Mishchenko fd390aae9d Extending MiniLUT to return attributes. 2018-02-11 17:14:07 -08:00
Alan Mishchenko f716948c27 Experiments with LUT mapping. 2018-02-10 15:45:54 -08:00
Alan Mishchenko f8d9fc3a9d Improvements to NDR to represent hierarchical designs. 2018-02-05 00:41:05 -08:00
Alan Mishchenko 28602ccf2c Improvements to NDR to represent hierarchical designs. 2018-02-05 00:39:10 -08:00
Alan Mishchenko 3202c2581e Improvements to NDR to represent hierarchical designs. 2018-02-05 00:37:39 -08:00
Alan Mishchenko 99ddb64095 Adding support of reading and writing designs using a new internal format. 2018-01-28 18:53:20 -08:00
Alan Mishchenko c8008383cf Experiments with circuit-based SAT. 2018-01-27 20:29:46 -08:00
Alan Mishchenko 20603c7585 Experiments with circuit-based SAT. 2018-01-27 15:25:31 -08:00
Alan Mishchenko f826956b07 Experiments with circuit-based SAT. 2018-01-27 14:33:49 -08:00
Alan Mishchenko 99c4dda767 Experiments with circuit-based SAT. 2018-01-27 14:05:00 -08:00
Alan Mishchenko 5158acb113 Experiments with circuit-based SAT. 2018-01-27 13:05:37 -08:00
Alan Mishchenko e4cd0d60f1 Experiments with SAT-based simulation. 2018-01-25 00:09:27 -08:00
Alan Mishchenko 066e8d1b17 Experiments with SAT-based simulation. 2018-01-23 19:45:17 -08:00
Alan Mishchenko 0ec5d2f7bc Fixed crash in &nf when there is no buffer gate. 2018-01-12 22:28:30 -08:00
Alan Mishchenko c3dccf3020 Corner-case bug fixed in CNF generation. 2017-12-28 13:32:02 -08:00
Alan Mishchenko feebac4156 Corner-case bug fixed in CNF generation. 2017-12-28 13:26:08 -08:00
Alan Mishchenko e5d8335268 Experiments with AIG-based simulation. 2017-12-05 09:49:02 -08:00
Alan Mishchenko 1743979b75 Adding switch -a to 'write_verilog' to write factored forms without XORs and MUXes. 2017-12-03 14:39:11 -08:00
Alan Mishchenko 3cc4080c55 Portability changes for gcc-6 suggested by Clifford. 2017-12-02 19:44:08 -08:00
Alan Mishchenko c681506b48 Improvements to AIG-based quantification. 2017-11-26 14:41:05 -08:00
Baruch Sterin d438d9c1b6 C++ compatibility: fix incompatible parameter list 2017-11-23 23:32:43 -08:00
Baruch Sterin d37cc72417 C++ compatibility: cast returned void* 2017-11-23 23:32:41 -08:00
Alan Mishchenko ecccfe0ed5 Experimental CEX minimization code. 2017-11-23 21:06:20 -08:00
Alan Mishchenko 203629fd0f Extracting CSAT interface and several cleanups. 2017-11-13 21:49:52 -08:00
Alan Mishchenko d85bc1dd68 Changes to make GIA structural hashing use a dedicated array instead of pObj->Value. 2017-11-13 18:50:04 -08:00
Alan Mishchenko 71d9a16714 Improvements to quantification. 2017-11-13 14:56:40 -08:00
Alan Mishchenko 5fd6dc0fca Profiling quantification and other changes. 2017-11-06 22:08:54 -08:00
Alan Mishchenko 716969190a Profiling quantification and other changes. 2017-11-06 16:43:32 -08:00
Alan Mishchenko e21052dfdd Improvements to quantification. 2017-10-29 12:24:07 -07:00
Bruno Schmitt 50e17ae0f4 Small fix. Garanteeing pPars is not NULL before checking pPars->fSlacks 2017-10-24 23:03:32 +02:00
Alan Mishchenko accf4825e5 Adding API to dump MiniAIG into a Verilog file and other small changes. 2017-10-22 15:44:13 -07:00
Alan Mishchenko 298ec14efa Integrating Glucose into &qbf. 2017-10-17 14:09:41 +09:00
Alan Mishchenko c1b4b79e99 Integrating Glucose into &qbf. 2017-10-17 13:53:48 +09:00
Alan Mishchenko f97b8d2882 Improvements to SAT based SOP computation. 2017-10-06 17:16:16 +03:00