mirror of https://github.com/YosysHQ/abc.git
Making sure duplicated inverters are not created.
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@ -305,6 +305,7 @@ Mini_Lut_t * Gia_ManToMiniLut( Gia_Man_t * pGia )
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Vec_Bit_t * vMarks;
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Gia_Obj_t * pObj, * pFanin;
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Vec_Int_t * vLeaves = Vec_IntAlloc( 16 );
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Vec_Int_t * vInvMap = Vec_IntStart( Gia_ManObjNum(pGia) );
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int i, k, iFanin, LutSize, nWords, Count = 0, pVars[16];
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word * pTruth;
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assert( Gia_ManHasMapping(pGia) );
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@ -361,12 +362,17 @@ Mini_Lut_t * Gia_ManToMiniLut( Gia_Man_t * pGia )
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pObj->Value = Mini_LutCreatePo( p, Gia_ObjFanin0(pObj)->Value );
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else // add inverter LUT
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{
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int Fanin = Gia_ObjFanin0(pObj)->Value;
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int LutInv = Mini_LutCreateNode( p, 1, &Fanin, (unsigned *)pTruth );
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int LutInv, Fanin = Gia_ObjFanin0(pObj)->Value;
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if ( (LutInv = Vec_IntEntry(vInvMap, Fanin)) == 0 )
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{
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LutInv = Mini_LutCreateNode( p, 1, &Fanin, (unsigned *)pTruth );
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Vec_IntWriteEntry( vInvMap, Fanin, LutInv );
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Count++;
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}
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pObj->Value = Mini_LutCreatePo( p, LutInv );
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Count++;
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}
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}
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Vec_IntFree( vInvMap );
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Vec_BitFree( vMarks );
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Gia_ObjComputeTruthTableStop( pGia );
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// set registers
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