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729 Commits

Author SHA1 Message Date
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko 76b00a2d3e Compilation problem with pow(). 2018-02-19 09:07:44 -08:00
Staf Verhaegen e4875df4e5 Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:54:38 +00:00
Alan Mishchenko accf4825e5 Adding API to dump MiniAIG into a Verilog file and other small changes. 2017-10-22 15:44:13 -07:00
Alan Mishchenko 1e1d41f3b8 Fix typo on the message reporting max output load. 2017-10-11 18:14:03 +07:00
Alan Mishchenko 396215532c Updates and bug fixes. 2017-10-04 12:37:38 +03:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 287f9efcce Maintenance and updates. 2017-09-20 19:27:46 -07:00
Alan Mishchenko 3a1032c151 Maintenance and updates. 2017-09-18 08:27:05 -07:00
Alan Mishchenko 2e56f44c66 Compiler warnings. 2017-07-22 11:41:17 +07:00
Alan Mishchenko 859e769f22 Synchronizing various data-structures. 2017-07-04 15:23:51 -07:00
Alan Mishchenko bf6a053c64 Saturating floating point computation. 2017-07-01 13:48:31 -07:00
Alan Mishchenko a1dd7e3fb0 Saturating floating point computation. 2017-06-29 17:58:43 -07:00
Alan Mishchenko d92bfbaddc Experiments with new network data-structure. 2017-03-20 23:45:03 -07:00
Alan Mishchenko 19ccaf21df Experiments with new network data-structure. 2017-03-19 21:51:03 -07:00
Heinz Riener a20002dab1 stringizing macro argument 2017-03-03 12:03:55 +01:00
Alan Mishchenko 7d5b1c572b Restoring constraint manager to read old constraint file by default (use 'read_constr -n' to read new format). 2017-02-25 13:34:54 -08:00
Alan Mishchenko afcbb09717 Corner-case bug-fix in library preprocessor for standard-cell mapping. 2017-02-05 10:43:07 -08:00
Alan Mishchenko dc7445e435 Typo. 2017-01-31 11:09:38 -08:00
Alan Mishchenko 8ad3d6bec8 Bug fixes by Clifford Wolf. 2017-01-08 03:10:42 +07:00
Alan Mishchenko 460167ec74 Compiler warnings. 2017-01-07 08:57:08 +07:00
Alan Mishchenko 3f2899d6ea Compiler warnings. 2016-12-31 22:00:26 +07:00
Alan Mishchenko d9fdd10960 Bug fix in Liberty parser. 2016-12-05 19:54:17 -08:00
Alan Mishchenko c6afb9db63 Equivalent fault detection code. 2016-11-09 21:17:44 -08:00
Alan Mishchenko 710f5cd4bc Memory leak in scl package. 2016-10-12 11:59:32 -07:00
Alan Mishchenko 693b587c5c Adding truth table occurrence counters for 'if -c'. 2016-08-08 18:20:05 -07:00
Alan Mishchenko 713976f2cf Enabled progress bar in the 'if' mapper (warning). 2016-08-08 12:38:21 -07:00
Alan Mishchenko a819e33c6f Enabled delay computation for the cut output using cut inputs. 2016-08-08 12:36:10 -07:00
Alan Mishchenko 473012aaf0 Enabled progress bar in the 'if' mapper. 2016-08-08 11:56:33 -07:00
Alan Mishchenko fd8eb8c855 Adding one argument to the delay-estimation API used for exact synthesis. 2016-07-31 13:31:57 -07:00
Alan Mishchenko cf91699e05 Infrastructure for using the results of exact SAT-based synthesis during mapping. 2016-07-29 16:34:47 -07:00
Alan Mishchenko fb33d69db8 Infrastructure for using the results of exact SAT-based synthesis during mapping. 2016-07-29 16:03:42 -07:00
Alan Mishchenko db43d6fbd8 Adding switch -P <num> to command 'cover'. 2016-06-14 20:43:50 -07:00
Alan Mishchenko 07d074fd88 New feature for area minimization in standard cell mapping. 2016-05-19 15:22:25 -07:00
Alan Mishchenko 7c089a3ac6 Factoring out library preprocessing code in &nf and putting it elsewhere. 2016-05-16 16:50:01 -07:00
Alan Mishchenko 20a2b0a0f2 Added switch 'read_genlib -n' to anonymize Genlib library. 2016-05-16 15:44:54 -07:00
Alan Mishchenko 53e8647719 Adding option to rehash AIG after mapping. 2016-04-27 18:33:23 -07:00
Alan Mishchenko 22a5ab19c8 Adding API to convert Genlib into a simple Liberty. 2016-03-11 00:15:13 +09:00
Alan Mishchenko 5a47990043 Disabling formula cleaner to avoid problems with reading GENLIB on some libraries. 2016-02-21 18:15:05 -08:00
Alan Mishchenko 59aea7639f Bug fix in liberty parser and change suggested by Clifford. 2016-02-07 12:54:13 -08:00
Alan Mishchenko 355865e81b GENLIB parsing bug, which led to a crash. 2016-02-06 12:07:42 -08:00
Alan Mishchenko 367b20f04d Fixing mismatch in the TLS flow induced by adding cell configs in the DSD manager. 2016-01-30 20:59:57 -08:00
Alan Mishchenko 87f6828d50 Adding support for delay/area tradeoff. 2016-01-13 12:13:54 -08:00
Alan Mishchenko a4f9776388 Consolidating timing manager Scl_Con_t and propagating changes. 2016-01-07 16:50:01 -08:00
Alan Mishchenko 15a891f97a Bug fix in constraint file reader. 2016-01-07 11:57:16 -08:00
Alan Mishchenko c158dd5a94 Migrating to using 32-bit timing representation in &nf. 2016-01-05 16:40:00 -08:00
Alan Mishchenko 19ad75f125 Migrating back to using 'float' in area-flow computation in &nf. 2016-01-05 14:05:07 -08:00
Alan Mishchenko 6642e40af5 Corner-case bug in 'read_profile'. 2015-12-22 22:09:25 -10:00
Alan Mishchenko 19586f105c Adding code to support gate profiles. 2015-12-14 00:44:33 -08:00
Alan Mishchenko e9abb0f489 Adding code to support gate profiles. 2015-12-07 01:31:41 -08:00