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3,602 Commits 27 Branches 57 Tags 58 MiB
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43 Commits

Author SHA1 Message Date
Alan Mishchenko 640100954a Updates to arithmetic verification. 2016-08-05 20:34:44 -07:00
Alan Mishchenko 2f86667326 Adding output range support to %blast. 2016-07-18 08:34:05 -07:00
Alan Mishchenko abdf39711f Several corner-case bugs in %read, &cec, and st. 2016-07-16 07:28:20 -07:00
Alan Mishchenko 00242f2fb2 New profiling features for word-level optimizations. 2016-06-04 17:31:15 -07:00
Alan Mishchenko c688d1b158 Improving SMT-LIB parser. 2016-05-23 10:42:53 -07:00
Alan Mishchenko 0f29f0aec9 Improving SMT-LIB parser. 2016-05-21 20:08:05 -07:00
Alan Mishchenko 34c5ac88d4 Improving SMT-LIB parser. 2016-05-20 20:38:43 -07:00
Alan Mishchenko 555ed0b158 Enabling AIGs without structural hashing. 2016-05-20 13:50:19 -07:00
Alan Mishchenko 236d412255 Experiments with CEC for arithmetic circuits. 2016-05-07 19:47:02 -07:00
Alan Mishchenko ee17cbbf4b Supporting negative and reverse ranges of word-level variables in Wlc. 2016-04-04 18:09:41 -07:00
Alan Mishchenko 65ee47c515 Supporting bit-wise XNOR operator in Wlc_Ntk_t. 2016-03-18 13:58:22 +08:00
Alan Mishchenko b2ad140adb Supporting complemented reduction operators. 2016-03-11 15:12:52 +09:00
Alan Mishchenko 74328f52da Supporting complemented reduction operators. 2016-03-10 23:03:53 +09:00
Alan Mishchenko 12fac91fba Supporting ~^ as equality operator in Wlc. 2016-03-04 09:17:39 +09:00
Alan Mishchenko c8962e94e2 Improving bit-blasting of a multiplier and squarer. 2016-02-13 18:51:42 -08:00
Alan Mishchenko e0616441b3 Adding support for a different bit-blasting of a multiplier and squarer. 2016-02-12 09:46:49 -08:00
Alan Mishchenko c81b6cb515 Supporting X-valued constants in Wlc_Ntk_t. 2016-02-02 15:43:19 -08:00
Alan Mishchenko 19586f105c Adding code to support gate profiles. 2015-12-14 00:44:33 -08:00
Alan Mishchenko 64afe6e9f8 Extending Verilog parser to handle 'default' in the case-statement. 2015-12-07 16:17:17 -08:00
Alan Mishchenko ea3133e3a4 Making ABC error out instead of crashing when non-standard range is given. 2015-08-03 16:24:10 -07:00
Alan Mishchenko d332e670a2 Improving Wlc_Ntk_t data-structure by extending bit-ranges up to 4B enabling printout of AND2 in '%ps -d'. 2015-07-16 17:37:48 -07:00
Alan Mishchenko e37bd1fb64 Improved bit-blasting of various operators in Wlc_Ntk_t; added SQRT operator (@). 2015-07-14 19:55:05 -07:00
Alan Mishchenko 6bd77858c5 Bug fixing in %blast when blasting MUX coming from always-statement. 2015-07-07 22:34:21 -07:00
Alan Mishchenko 8efc9cb7a9 Bug fixing in %blast when blasting mod operator (handling zero divisor). 2015-07-07 15:38:54 -07:00
Alan Mishchenko a26d8621f0 Add warnings to %read about 3-arge ops and non-zero-based ranges. 2015-06-23 15:53:41 -07:00
Alan Mishchenko 68467cfff7 Fixed a typo in variable names. 2015-02-07 22:29:14 -08:00
Alan Mishchenko 55c5c1b58f Added SMT parser for Wlc_Ntk_t. 2015-02-07 22:05:02 -08:00
Alan Mishchenko 416cc3b2ae Outputting initial state in Wlc_Ntk_t. 2015-01-25 11:21:36 -08:00
Alan Mishchenko 3dd4e356fc Fix in deriving the init values for Wlc_Ntk_t. 2015-01-22 15:16:45 -08:00
Alan Mishchenko cf83242458 Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t. 2015-01-21 17:45:48 -08:00
Alan Mishchenko ffc7b60d2d Support of init-state in AIGs derived from word-level designs in Wlc_Ntk_t. 2015-01-21 17:43:46 -08:00
Alan Mishchenko 1d20dea11b Induced bug fix in bitblasting of rotation operator. 2014-11-29 19:34:47 -08:00
Alan Mishchenko cc37fb9573 Improvements to word-level network package. 2014-11-14 20:12:20 -08:00
Alan Mishchenko a34183790f Enabling AIGs with boxes for word-level and sequential designs. 2014-11-13 18:28:25 -08:00
Alan Mishchenko f0044175ee Improvements to the parser. 2014-10-10 19:17:19 -07:00
Alan Mishchenko 69bd355467 Support for sequential designs in word-level Verilog. 2014-09-26 16:11:36 -07:00
Alan Mishchenko ffaad9ba10 Bug fix in handling MUXes in Verilog parser, induced by recent changes. 2014-09-24 09:05:40 -04:00
Alan Mishchenko a4d5a9b5bc Added support of word-level MUXes represented as 'always'-statements. 2014-09-24 00:22:18 -04:00
Alan Mishchenko 043cfcd775 Concurrency for Boolean matching. 2014-09-18 11:46:14 -07:00
Alan Mishchenko 69827a5a88 Improvements to word-level Verilog parser. 2014-09-17 15:20:04 -07:00
Alan Mishchenko ffd77ffedd Improvements to word-level Verilog parser. 2014-09-17 15:14:17 -07:00
Alan Mishchenko ec0b9b6b6e Improvements to word-level Verilog parser. 2014-09-16 22:08:22 -07:00
Alan Mishchenko dcb7d0d3fc New word-level representation package. 2014-09-12 13:40:48 -07:00