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37 Commits

Author SHA1 Message Date
Alan Mishchenko 57966de4b4 Adding flag to skip two-output cells in "read_lib". 2025-05-14 17:01:48 -07:00
Alan Mishchenko 3ddd46131c Updating "read_lib" to output all gates when gain-based modeling is used. 2024-09-05 17:53:13 -07:00
Alan Mishchenko 99e0e37da6 Added switch -p in "read_lib" to skip writing cell prefix. 2024-04-14 09:51:00 -07:00
Alan Mishchenko 0c719ab69e Adding procedure to merge two libraries. 2023-09-08 14:23:14 +07:00
Ethan Mahintorabi 503c4a34b0
map: Adds a user configurable dont_use flag to liberty 
This flag (-X <glob>) will allow a user to set this flag
multiple times with a glob pattern to exclude cells that
user doesn't want to show up in a mapped netlist.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-08-14 18:19:20 +00:00
Alan Mishchenko 710f5cd4bc Memory leak in scl package. 2016-10-12 11:59:32 -07:00
Alan Mishchenko 22a5ab19c8 Adding API to convert Genlib into a simple Liberty. 2016-03-11 00:15:13 +09:00
Alan Mishchenko f7c969ca66 Improvements to timing optimization. 2015-11-11 23:12:05 -08:00
Alan Mishchenko 3c9f7d2bc8 Extending and improving timing manager. 2015-11-08 19:59:34 -08:00
Alan Mishchenko 96d8f899d9 Extending and improving timing manager. 2015-11-08 11:44:37 -08:00
Alan Mishchenko 78951b4c6f Improvements to Scl_Lib/SC_Cell data-structure. 2015-09-24 12:12:36 -07:00
Alan Mishchenko 5bf0f86450 New switch in 'read_lib' to replace gate/pin names by short strings. 2015-08-24 17:40:20 -07:00
Alan Mishchenko aadfea8b4d Integrating barrier buffers. 2014-12-13 12:37:04 -08:00
Alan Mishchenko 6d0b555dab Support for leakage power in Liberty parser and sizer. 2014-09-16 16:44:51 -07:00
Alan Mishchenko 48912a2247 Fixing Liberty parser to handle 'scalar' delay/slew tables. 2014-02-06 12:22:30 -08:00
Alan Mishchenko 00efa68053 Several changes to allow Liberty files without delay info. 2013-11-21 12:58:13 -08:00
Alan Mishchenko 4774dc56fe Fixing the wire-load approximation problem. 2013-11-07 10:24:47 -08:00
Alan Mishchenko 1692c1a57a Improvements to buffering and sizing. 2013-10-13 23:08:52 -07:00
Alan Mishchenko 89cab3adec Normalization of slew/load values. 2013-10-13 20:55:24 -07:00
Alan Mishchenko c6b80ffc13 Normalization of slew/load values. 2013-10-13 19:11:49 -07:00
Alan Mishchenko e01174c6db Bug fixes in the library processing,. 2013-10-02 18:22:14 -07:00
Alan Mishchenko a2d97cf2b6 Debugging and finetuning the flow. 2013-09-17 16:43:42 -07:00
Alan Mishchenko 7d3976a763 Unifying standard cell library representations. 2013-09-17 13:16:20 -07:00
Alan Mishchenko ff5d3591d1 Infrastructure to support full Liberty format and unitification of library representations. 2013-09-15 18:23:49 -07:00
Alan Mishchenko ae27704c13 Integrated buffering and sizing. 2013-08-11 11:35:22 -07:00
Alan Mishchenko 6c4252c5c9 Integrated buffering and sizing. 2013-08-10 18:11:09 -07:00
Alan Mishchenko 573d6d7ab7 Enable wire load estimation in buffering/sizing. 2013-08-10 10:27:55 -07:00
Alan Mishchenko 4af5587cbf Integrated buffering and sizing. 2013-08-09 21:44:18 -07:00
Alan Mishchenko 633db0f4ad Improvements to buffering and sizing. 2013-08-09 17:54:18 -07:00
Alan Mishchenko 95684b044a Improvements to buffering and sizing. 2013-08-09 11:15:20 -07:00
Alan Mishchenko 881b2ec46f Integrated buffering and sizing. 2013-08-08 18:23:00 -07:00
Alan Mishchenko 8576e4b440 Improvements to buffering and sizing. 2013-08-06 22:51:39 -07:00
Alan Mishchenko 1558fe6110 Adding code to estimate buffer trees. 2013-08-05 10:45:06 -07:00
Alan Mishchenko 1dca7458f3 Improved buffering. 2013-07-29 18:55:13 -07:00
Alan Mishchenko 84c0b9d69b Tuning standard-cell mapping flow. 2013-07-23 16:15:03 -07:00
Alan Mishchenko f392645daf Generating GENLIB library from SCL. 2013-07-22 13:25:51 -07:00
Alan Mishchenko fd28deefc7 Restructuring gate-sizing code trying to separate timing analysis. 2013-07-21 17:55:15 -07:00