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4277 Commits

Author SHA1 Message Date
Alan Mishchenko 53e7d1f9ef Adding switch 'scorr -f' to dump inductive invariant as an AIG. 2018-03-22 10:10:09 -07:00
Alan Mishchenko 69416b7ca1 Temporary bug fix for signal names in WLC (correction). 2018-03-21 20:52:36 -07:00
Alan Mishchenko d410faf85c Temporary bug fix for signal names in WLC. 2018-03-21 20:18:17 -07:00
Baruch Sterin c339c6f7f1 Continuos integration support of both Travis CI (Linux and macOS) and Appveyor (Windows) 2018-03-11 05:08:57 -07:00
Alan Mishchenko 3d16d44cff Bug fix in blasting with boxes. 2018-03-06 23:21:49 -08:00
Alan Mishchenko 48e128aa72 Extending primitives supported by WLC. 2018-03-03 17:57:30 -08:00
Alan Mishchenko f6b9cc013d Adding parameters and improvements to %blast. 2018-02-28 19:38:55 -08:00
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko 33971604cf Adding support for adders with carry-in in WLC and NDR. 2018-02-24 09:50:24 -08:00
Alan Mishchenko fe56e29d44 Bug fix in NDR handling. 2018-02-20 16:56:52 -08:00
Alan Mishchenko 836f901fca Merge two branches. 2018-02-20 16:05:08 -08:00
Alan Mishchenko b2055bd637 Improvements to circuit based solver. 2018-02-20 16:00:58 -08:00
Bruno Schmitt eb4bee3e1d Small fix in satoko. 2018-02-20 20:31:39 +01:00
Alan Mishchenko 76b00a2d3e Compilation problem with pow(). 2018-02-19 09:07:44 -08:00
Alan Mishchenko 1d1b11cb65 Improvements to circuit based solver. 2018-02-17 13:10:48 -08:00
Alan Mishchenko fd390aae9d Extending MiniLUT to return attributes. 2018-02-11 17:14:07 -08:00
Alan Mishchenko f716948c27 Experiments with LUT mapping. 2018-02-10 15:45:54 -08:00
Alan Mishchenko c6bce9c20e Fixing input swapping issue in MUXes derived from NDR. 2018-02-07 09:02:28 -08:00
Alan Mishchenko e839091ba0 Suggested fix to compile on FreeBSD. 2018-02-05 19:00:46 -08:00
Alan Mishchenko f8d9fc3a9d Improvements to NDR to represent hierarchical designs. 2018-02-05 00:41:05 -08:00
Alan Mishchenko 28602ccf2c Improvements to NDR to represent hierarchical designs. 2018-02-05 00:39:10 -08:00
Alan Mishchenko 3202c2581e Improvements to NDR to represent hierarchical designs. 2018-02-05 00:37:39 -08:00
Alan Mishchenko 00fb1d706b Suggested fix to compile on FreeBSD. 2018-02-04 21:09:33 -08:00
Alan Mishchenko 30a06d002a Adding support of reading and writing designs using a new internal format (bug fix). 2018-01-29 17:01:01 -08:00
Alan Mishchenko 99ddb64095 Adding support of reading and writing designs using a new internal format. 2018-01-28 18:53:20 -08:00
Alan Mishchenko c8008383cf Experiments with circuit-based SAT. 2018-01-27 20:29:46 -08:00
Alan Mishchenko 20603c7585 Experiments with circuit-based SAT. 2018-01-27 15:25:31 -08:00
Alan Mishchenko f826956b07 Experiments with circuit-based SAT. 2018-01-27 14:33:49 -08:00
Alan Mishchenko 99c4dda767 Experiments with circuit-based SAT. 2018-01-27 14:05:00 -08:00
Alan Mishchenko 5158acb113 Experiments with circuit-based SAT. 2018-01-27 13:05:37 -08:00
Alan Mishchenko e4cd0d60f1 Experiments with SAT-based simulation. 2018-01-25 00:09:27 -08:00
Alan Mishchenko 066e8d1b17 Experiments with SAT-based simulation. 2018-01-23 19:45:17 -08:00
Alan Mishchenko 67e820a5eb Updates to exact synthesis commands. 2018-01-22 14:28:49 -08:00
Alan Mishchenko 6274498e01 Updates to exact synthesis commands. 2018-01-19 14:03:24 -08:00
Alan Mishchenko c2b6e03c61 Backing up node's truth-table to make sure it is not destroyed while deriving AIG. 2018-01-19 12:22:48 -08:00
Alan Mishchenko 0ec5d2f7bc Fixed crash in &nf when there is no buffer gate. 2018-01-12 22:28:30 -08:00
Alan Mishchenko 29895ca2f8 Merged in Fatsie/abc/liberty_value_expression (pull request #87) 
Allow expression in value in liberty file
 2018-01-05 06:47:44 +00:00
Alan Mishchenko 7d781c37e8 New command 'testexact'. 2018-01-04 22:35:11 -08:00
Alan Mishchenko 834e248019 New command 'testexact'. 2018-01-04 22:33:29 -08:00
Staf Verhaegen e513afae09 Created new branch liberty_value_expression 2018-01-04 22:05:57 +00:00
Staf Verhaegen e4875df4e5 Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:54:38 +00:00
Alan Mishchenko f3dcf87cea New exact synthesis command 'allexact'. 2017-12-30 16:13:52 -08:00
Alan Mishchenko 75d334a0df New exact synthesis command 'allexact'. 2017-12-28 23:05:36 -08:00
Alan Mishchenko 7d7ce3ecd0 New exact synthesis command 'allexact'. 2017-12-28 23:04:24 -08:00
Alan Mishchenko c3dccf3020 Corner-case bug fixed in CNF generation. 2017-12-28 13:32:02 -08:00
Alan Mishchenko feebac4156 Corner-case bug fixed in CNF generation. 2017-12-28 13:26:08 -08:00
Alan Mishchenko 680af1891b Bug fix in 'write_aiger_cex'. 2017-12-20 15:41:39 -08:00
Alan Mishchenko c7b65a15d3 Adding parameter structure to 'twoexact' and 'lutexact'. 2017-12-06 15:09:11 -08:00
Alan Mishchenko 93b96fc35c An improvement to 'twoexact' and 'lutexact'. 2017-12-06 14:34:03 -08:00
Alan Mishchenko c6b962efc8 An improvement to 'twoexact' and 'lutexact'. 2017-12-06 13:51:10 -08:00