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5853 Commits

Author SHA1 Message Date
alanminko 0dc5524b80
Merge pull request #425 from MyskYko/fix3 
fix cadical
 2025-07-07 03:44:24 -07:00
MyskYko 6e130c15a3 fix setnvars 2025-06-20 15:28:27 -07:00
MyskYko 9ea1aaa3cf fix comments 2025-06-20 14:45:50 -07:00
MyskYko a5156f257e fix cadical 2025-06-20 13:40:04 -07:00
Alan Mishchenko beff7f1b34 Temporary fix of the compilation problem related to sorting objects by level in rewiring. 2025-06-19 14:32:10 +07:00
alanminko 83824878e3
Merge pull request #422 from MyskYko/fix 
fix amap -m
 2025-06-17 21:20:28 -07:00
alanminko da52efecdc
Merge pull request #423 from MyskYko/fix2 
fix a bug when yosys constants are already declared
 2025-06-17 21:19:55 -07:00
MyskYko e9845e534a fix a bug when yosys constants are already declared 2025-06-17 16:41:43 -07:00
MyskYko f443db4a24 fix amap -m 2025-06-16 10:27:33 -07:00
Alan Mishchenko 6463f11625 Fixing pointer-dependent behavior during BDD variable reordering. 2025-06-07 12:52:23 -07:00
alanminko 44f3265e8b
Merge pull request #397 from phyzhenli/patch-1 
fix typo
 2025-06-07 10:39:21 -07:00
alanminko afae379366
Merge pull request #419 from mikesinouye/multilib 
Prevent merged scl filename size from growing unbounded.
 2025-06-07 10:38:15 -07:00
alanminko 5cf5a8d9f5
Merge pull request #412 from tklam/feature/support_verilog_gate_name 
Support primitive gates with names in Verilog netlist
 2025-06-07 10:38:03 -07:00
alanminko d4358ec80c
Merge pull request #399 from wjrforcyber/gtest_refactor 
Refactor(gtest): Remove duplicate libgtest.a
 2025-06-07 10:37:53 -07:00
Mike Inouye a4064b8b73 Prevent merged scl filename size from growing unbounded, which limits upper bound of files loaded. 2025-05-30 18:14:47 +00:00
alanminko 0a55186553
Merge pull request #416 from chenjunhao0315/master 
patch rewire with empty name
 2025-05-25 22:27:43 -07:00
Alan Mishchenko 1f98c28011 Improved cascade printout in "lutcasdec". 2025-05-25 22:24:33 -07:00
Alan Mishchenko 301b46e3c1 Fixiing BLIF reader to read Yosys constants. 2025-05-25 18:45:59 -07:00
jiunhaochen 04161dfda8 patch rewire with empty name 2025-05-26 01:44:04 +08:00
Alan Mishchenko 0ae04514cd Work-around for a bug in "lutcasdec". 2025-05-22 23:56:40 -07:00
Alan Mishchenko 716314d835 Generating AIGs for adders. 2025-05-22 23:56:13 -07:00
Alan Mishchenko 32fe49b6d1 New commands for reading/writing mini-mapping for AIGs. 2025-05-21 21:57:51 -07:00
Alan Mishchenko e1a1994292 Extending "&cofs" to handle multi-output AIGs. 2025-05-21 21:30:58 -07:00
alanminko 0c155952bf
Merge pull request #415 from HAHHHD/master 
add clause pushing with blocking
 2025-05-20 16:37:20 -07:00
Alan Mishchenko 3bd7bac552 Improvements to "lutcasdec". 2025-05-20 16:17:43 -07:00
HAHHHD e20c484ee1 add clause pushing with blocking 2025-05-20 15:04:15 -07:00
Alan Mishchenko c5edc566ff Improvements to "lutcasdec". 2025-05-20 14:28:07 -07:00
Alan Mishchenko 29c8d3eacf Improvements to "lutcasdec". 2025-05-20 10:41:47 -07:00
Alan Mishchenko 9bb736acee Improvements to "lutcasdec". 2025-05-20 06:39:28 -07:00
Alan Mishchenko c398b06740 Experiments with decomposition. 2025-05-20 06:08:46 -07:00
Alan Mishchenko 240bf58f90 Updating "short_names" and BDD profiling. 2025-05-19 10:24:56 -07:00
Alan Mishchenko 916f70058e Updating script runner. 2025-05-18 14:05:50 -07:00
Alan Mishchenko 0b1d7c6d0f Supporting structural choices in rewiring. 2025-05-18 13:37:30 -07:00
Alan Mishchenko 5daa0c347e Small changes to "lutcasdec". 2025-05-16 17:23:32 -07:00
Alan Mishchenko 57966de4b4 Adding flag to skip two-output cells in "read_lib". 2025-05-14 17:01:48 -07:00
Alan Mishchenko d34821e768 Skipping cells with more than two outputs in "read_lib". 2025-05-14 14:17:05 -07:00
Alan Mishchenko 078debff4e Adding print-out of LUT mapping stats. 2025-05-13 22:49:55 -07:00
Alan Mishchenko d245305393 Improvements to "lutcasdec". 2025-05-13 19:21:56 -07:00
tklam 9545b79e0e support primitive gates with names in Verilog netlist 2025-05-12 10:20:13 -04:00
Alan Mishchenko c85f007f75 Convert buffers to .short lines in BLIF. 2025-05-09 18:16:37 -07:00
Alan Mishchenko 490bb92a8c Fixing the Yosys script used to read a mapped netlist. 2025-05-09 17:17:26 -07:00
Alan Mishchenko a42e6ecd23 Fixing a bug in "read_lib". 2025-05-09 17:13:40 -07:00
Alan Mishchenko 9dc7ade063 Adding a switch to read mapped Verilog using command %yosys. 2025-05-09 11:47:26 -07:00
Alan Mishchenko 71b60a9830 Updating &stochsyn. 2025-05-07 19:53:53 -07:00
Alan Mishchenko 4560597b31 Utility to duplicate inputs. 2025-05-07 16:53:51 -07:00
Alan Mishchenko 49d9252f90 Updating the way min col mult is reported in lutcasdec. 2025-05-05 09:03:41 -07:00
Alan Mishchenko 5e54ef3aff Adding printout of flops. 2025-05-03 18:15:11 -07:00
Alan Mishchenko f9e4d06806 Column multiplicity statistics 2025-05-02 08:18:12 -07:00
Alan Mishchenko 692b0c6908 Printout of column multiplicity statistics. 2025-05-02 08:13:20 -07:00
Alan Mishchenko 75adf123f6 Adding new feature to &nf. 2025-05-01 22:41:49 -07:00