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5579 Commits

Author SHA1 Message Date
WWFUG 67a2b97cf0 added -I options in &bmiter 2023-11-08 19:00:03 +08:00
Alan Mishchenko 04dba9eed9 Adding callback for wire caps during sizing. 2023-11-06 17:35:41 -08:00
Allen Ho 50010139ef why 2023-11-06 18:37:40 +08:00
Allen Ho ba64d6118b out-side box matching 2023-10-30 15:09:01 -07:00
Alan Mishchenko 5de12aa6b3 Experiments with SAT solving. 2023-10-23 11:30:44 -07:00
Alan Mishchenko 1bf21626c0 Bug fix. 2023-10-23 11:04:35 -07:00
Alan Mishchenko 76e8d21aaf Printout changes. 2023-10-23 10:48:43 -07:00
Alan Mishchenko 538ecb4515 Updating printouts. 2023-10-23 09:38:24 -07:00
Alan Mishchenko 01ad71b26f Experiments with verification. 2023-10-23 09:38:08 -07:00
Alan Mishchenko 8dbf8965fd Adding batch option to "scrgen". 2023-10-23 09:37:04 -07:00
Alan Mishchenko 652a0aaef7 Compiler warning. 2023-10-20 22:42:40 -07:00
Alan Mishchenko 72b423ba14 Experiments with SAT solving. 2023-10-20 20:53:43 -07:00
Miodrag Milanovic 896e5e7ded disable command history 2023-10-13 14:28:47 +02:00
Alan Mishchenko 3c4c558656 Experiment with script generation. 2023-10-02 16:47:37 -07:00
Alan Mishchenko 65ccd3cc69 Enabled literal remapping. 2023-09-29 16:07:29 -07:00
Alan Mishchenko d971e3ecff Updating windows project file. 2023-09-28 07:17:42 -07:00
Alan Mishchenko cc636a0d83 Experiments with verification. 2023-09-28 06:40:57 -07:00
Alan Mishchenko 0f11580fce Experiments with retiming. 2023-09-24 22:18:45 +08:00
Alan Mishchenko 4d1618f600 Enable dumping Verilog with assign-statements. 2023-09-21 11:08:43 +08:00
Alan Mishchenko 73dac01c15 Warning regarding PathMatchSpec() on Windows. 2023-09-21 11:08:16 +08:00
Allen Ho 31ad17fa1a add abc9RecoverBoundary 2023-09-20 14:23:47 +08:00
Alan Mishchenko 7fd4b01fb3 Automatic script file generation. 2023-09-18 16:30:09 +08:00
Alan Mishchenko 09b0295c1a Adding aliases for some commands. 2023-09-18 16:27:54 +08:00
Alan Mishchenko 9399faac48 Improvements to &gen_hie. 2023-09-17 12:40:33 +08:00
Alan Mishchenko da635a2995 Updating .gitignore. 2023-09-17 12:18:12 +08:00
Alan Mishchenko 2f5b81119b Experiments with retiming. 2023-09-17 12:17:27 +08:00
Alan Mishchenko 4222921d61 Revert "Merge pull request #247 from QuantamHD/abc_unit_tests" 
This reverts commit d91a2a049a, reversing
changes made to 475c8dad8e.
 2023-09-17 11:29:26 +08:00
alanminko d91a2a049a
Merge pull request #247 from QuantamHD/abc_unit_tests 
Adds unit testing framework to ABC
 2023-09-16 15:41:56 +08:00
Alan Mishchenko 475c8dad8e Compiler problem. 2023-09-16 07:13:10 +08:00
alanminko 2800847a16
Merge pull request #249 from Yu-Maryland/master 
AIG augmentation
 2023-09-16 07:08:23 +08:00
Cunxi Yu 1261f71248
Merge branch 'berkeley-abc:master' into master 2023-09-15 13:25:27 -07:00
Alan Mishchenko 318d5cb54b Do not create spec outputs in the boundary miter. 2023-09-15 23:10:42 +08:00
Alan Mishchenko 57cc2bd089 Compiler problem. 2023-09-15 22:51:11 +08:00
Alan Mishchenko 09013f3a6e New command &gen_hie to generate hierarchical designs. 2023-09-15 22:44:31 +08:00
Ethan Mahintorabi 7d80ea5cf9
Adds unit testing framework to ABC 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-09-13 18:24:01 +00:00
Catherine daad9ede01 Add WASI support in Gia_StochProcessOne. 2023-09-13 14:59:58 +01:00
Catherine 89a5395fc6 Add WASI support in Cnf_RunSolverOnce and Cnf_SplitCnfFile. 2023-09-13 13:47:32 +01:00
Catherine 6b66b81722 Add WASI support in Abc_ThreadClock. 2023-09-13 12:33:30 +01:00
alanminko 79456fadde
Merge pull request #246 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2023-09-12 11:30:53 +07:00
wjrforcyber 3a53a950aa Refactor(Typo): Typo update on buffer 2023-09-12 11:57:18 +08:00
wjrforcyber 7fe7449685 Refactor(Typo):Typo update on dnsize 2023-09-12 10:40:59 +08:00
Miodrag Milanovic 9537f391fd Merge remote-tracking branch 'upstream/master' into yosys-experimental 2023-09-11 16:16:47 +02:00
Alan Mishchenko 20f9095cf2 Adding link to the fork of ABC with Agdmap. 2023-09-11 12:14:57 +07:00
Alan Mishchenko 1153b3b6b9 Commenting out an assert that signals a non-critical formance bug. 2023-09-11 12:12:52 +07:00
Alan Mishchenko 1ffdbbbebe Corner-case bug fix. 2023-09-11 10:46:38 +07:00
Alan Mishchenko 588122dc72 Writing an interface module when dumping Verilog. 2023-09-11 09:44:22 +07:00
Alan Mishchenko 6d866dab6b Updating command "time" to report wall time. 2023-09-09 10:06:33 +07:00
Alan Mishchenko a4755a37cb Experiments with CEC. 2023-09-08 22:42:41 +07:00
Alan Mishchenko 55aba1731c Fixing a typo. 2023-09-08 19:57:45 +07:00
Alan Mishchenko f844fb1057 Command to add one flop to the design. 2023-09-08 16:46:14 +07:00