mirror of https://github.com/YosysHQ/abc.git
Updating LUT cascade generation to support flexible inputs.
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309282601e
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d8219265fc
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@ -160,13 +160,23 @@ char * Gia_LutCasPerm( int nVars, int nLuts, int LutSize )
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Gia_LutCasSort( pRes + i * LutSize, 1, LutSize-1 );
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return pRes;
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}
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int Gia_ManGenLutCas_rec( Gia_Man_t * pNew, Vec_Int_t * vCtrls, int iCtrl, Vec_Int_t * vDatas, int Shift )
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int Gia_ManGenLutCas_rec( Gia_Man_t * pNew, Vec_Int_t * vCtrls, int iCtrl, Vec_Int_t * vDatas, int Shift, int Offset )
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{
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if ( iCtrl-- == 0 )
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return Vec_IntEntry( vDatas, Shift );
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int iLit0 = Gia_ManGenLutCas_rec( pNew, vCtrls, iCtrl, vDatas, Shift );
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int iLit1 = Gia_ManGenLutCas_rec( pNew, vCtrls, iCtrl, vDatas, Shift + (1<<iCtrl));
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return Gia_ManAppendMux( pNew, Vec_IntEntry(vCtrls, iCtrl), iLit1, iLit0 );
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int iLit0 = Gia_ManGenLutCas_rec( pNew, vCtrls, iCtrl, vDatas, Shift, Offset );
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int iLit1 = Gia_ManGenLutCas_rec( pNew, vCtrls, iCtrl, vDatas, Shift + (1<<iCtrl), Offset );
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return Gia_ManAppendMux( pNew, Vec_IntEntry(vCtrls, iCtrl+Offset), iLit1, iLit0 );
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}
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int Gia_ManGenWire( Gia_Man_t * pNew, Vec_Int_t * vCtrls, Vec_Int_t * vParams2, int iParam2 )
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{
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int nVars = Vec_IntSize(vCtrls);
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int nBits = Abc_Base2Log(nVars);
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while ( Vec_IntSize(vCtrls) < (1 << nBits) )
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Vec_IntPush( vCtrls, 0 );
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int iRes = Gia_ManGenLutCas_rec( pNew, vParams2, nBits, vCtrls, 0, iParam2 );
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Vec_IntShrink( vCtrls, nVars );
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return iRes;
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}
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Gia_Man_t * Gia_ManGenLutCas( Gia_Man_t * p, char * pPermStr, int nVars, int nLuts, int LutSize, int Seed, int fVerbose )
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{
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@ -181,25 +191,39 @@ Gia_Man_t * Gia_ManGenLutCas( Gia_Man_t * p, char * pPermStr, int nVars, int nLu
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int fOwnPerm = (pPermStr == NULL);
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char * pPerm = fOwnPerm ? Gia_LutCasPerm( nVars, nLuts, LutSize ) : pPermStr;
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int nParams = nLuts * (1 << LutSize);
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// count how many variables are unassigned in the permutation
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int nParams2 = 0;
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for ( int v = 0; v < strlen(pPerm); v++ )
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if ( pPerm[v] == '*' )
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nParams2 += Abc_Base2Log(nVars);
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if ( fVerbose )
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printf( "Generating AIG with %d parameters and %d inputs using fanin assignment %s.\n", nParams, nVars, pPerm );
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printf( "Generating AIG with %d parameters (%d functional + %d structural) and %d inputs using fanin assignment \"%s\".\n",
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nParams+nParams2, nParams, nParams2, nVars, pPerm );
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Gia_Man_t * pNew = Gia_ManStart( nParams + nVars );
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pNew->pName = Abc_UtilStrsav( pPerm );
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Vec_Int_t * vDatas = Vec_IntAlloc( nParams );
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Vec_Int_t * vWires = Vec_IntAlloc( nParams2 );
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Vec_Int_t * vCtrls = Vec_IntAlloc( nVars );
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for ( int i = 0; i < nParams; i++ )
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Vec_IntPush( vDatas, Gia_ManAppendCi(pNew) );
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for ( int i = 0; i < nParams2; i++ )
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Vec_IntPush( vWires, Gia_ManAppendCi(pNew) );
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for ( int i = 0; i < nVars; i++ )
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Vec_IntPush( vCtrls, Gia_ManAppendCi(pNew) );
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Vec_Int_t * vLits = Vec_IntStart( LutSize );
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Vec_IntWriteEntry( vLits, 0, Vec_IntEntry(vCtrls, (int)(pPerm[0]-'a')) );
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Vec_IntWriteEntry( vLits, 0, pPerm[0] == '*' ? Gia_ManGenWire(pNew, vCtrls, vWires, 0) : Vec_IntEntry(vCtrls, (int)(pPerm[0]-'a')) );
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int iWireVars = pPerm[0] == '*' ? Abc_Base2Log(nVars) : 0;
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char * pCur = pPerm;
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for ( int i = 0; i < nLuts; i++ ) {
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assert( i == 0 || *pCur == '_' );
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pCur++;
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for ( int k = 1; k < LutSize; k++ )
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Vec_IntWriteEntry( vLits, k, Vec_IntEntry(vCtrls, (int)(*pCur++ - 'a')) );
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Vec_IntWriteEntry( vLits, 0, Gia_ManGenLutCas_rec(pNew, vLits, LutSize, vDatas, i * (1 << LutSize)) );
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for ( int k = 1; k < LutSize; k++ ) {
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Vec_IntWriteEntry( vLits, k, *pCur == '*' ? Gia_ManGenWire(pNew, vCtrls, vWires, iWireVars) : Vec_IntEntry(vCtrls, (int)(*pCur - 'a')) );
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iWireVars += *pCur++ == '*' ? Abc_Base2Log(nVars) : 0;
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}
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Vec_IntWriteEntry( vLits, 0, Gia_ManGenLutCas_rec(pNew, vLits, LutSize, vDatas, i * (1 << LutSize), 0) );
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}
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assert( iWireVars == nParams2 );
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// if the AIG is given, create a miter
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int iLit = Vec_IntEntry(vLits, 0);
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if ( p ) {
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@ -218,6 +242,7 @@ Gia_Man_t * Gia_ManGenLutCas( Gia_Man_t * p, char * pPermStr, int nVars, int nLu
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Gia_ManAppendCo( pNew, iLit );
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Vec_IntFree( vDatas );
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Vec_IntFree( vCtrls );
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Vec_IntFree( vWires );
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Vec_IntFree( vLits );
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if ( fOwnPerm )
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ABC_FREE( pPerm );
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