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https://github.com/YosysHQ/abc.git
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Generation of barrier-buffers for hierarchical design.
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+35
-10
@@ -86,7 +86,7 @@ int Abc_NodeStrashToGia( Gia_Man_t * pNew, Abc_Obj_t * pNode )
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SeeAlso []
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***********************************************************************/
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void Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Abc_Ntk_t * pNtk, int * pCounter )
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void Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Abc_Ntk_t * pNtk, int * pCounter, Vec_Int_t * vBufs )
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{
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Vec_Ptr_t * vDfs = (Vec_Ptr_t *)pNtk->pData;
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Abc_Obj_t * pObj, * pTerm;
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@@ -98,6 +98,7 @@ void Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Abc_Ntk_t * pNtk, int *
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Abc_ObjFanout0(pObj)->iTemp = Abc_NodeStrashToGia( pNew, pObj );
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else
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{
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int iBufStart = Gia_ManBufNum(pNew);
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Abc_Ntk_t * pModel = (Abc_Ntk_t *)pObj->pData;
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assert( !Abc_ObjIsLatch(pObj) );
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assert( Abc_NtkPiNum(pModel) == Abc_ObjFaninNum(pObj) );
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@@ -106,27 +107,39 @@ void Gia_ManFlattenLogicHierarchy_rec( Gia_Man_t * pNew, Abc_Ntk_t * pNtk, int *
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Abc_ObjForEachFanin( pObj, pTerm, k )
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{
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assert( Abc_ObjIsNet(Abc_ObjFanin0(pTerm)) );
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// Abc_ObjFanout0(Abc_NtkPi(pModel, k))->iTemp = Gia_ManAppendBuf( pNew, Abc_ObjFanin0(pTerm)->iTemp );
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Abc_ObjFanout0(Abc_NtkPi(pModel, k))->iTemp = Abc_ObjFanin0(pTerm)->iTemp;
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}
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Gia_ManFlattenLogicHierarchy_rec( pNew, pModel, pCounter );
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if ( vBufs )
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Abc_ObjForEachFanin( pObj, pTerm, k )
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Abc_ObjFanout0(Abc_NtkPi(pModel, k))->iTemp = Gia_ManAppendBuf( pNew, Abc_ObjFanout0(Abc_NtkPi(pModel, k))->iTemp );
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Gia_ManFlattenLogicHierarchy_rec( pNew, pModel, pCounter, vBufs );
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if ( vBufs )
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Abc_ObjForEachFanout( pObj, pTerm, k )
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Abc_ObjFanin0(Abc_NtkPo(pModel, k))->iTemp = Gia_ManAppendBuf( pNew, Abc_ObjFanin0(Abc_NtkPo(pModel, k))->iTemp );
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Abc_ObjForEachFanout( pObj, pTerm, k )
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{
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assert( Abc_ObjIsNet(Abc_ObjFanout0(pTerm)) );
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// Abc_ObjFanout0(pTerm)->iTemp = Gia_ManAppendBuf( pNew, Abc_ObjFanin0(Abc_NtkPo(pModel, k))->iTemp );
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Abc_ObjFanout0(pTerm)->iTemp = Abc_ObjFanin0(Abc_NtkPo(pModel, k))->iTemp;
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}
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// save buffers
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if ( vBufs == NULL )
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continue;
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Vec_IntPush( vBufs, iBufStart );
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Vec_IntPush( vBufs, Abc_NtkPiNum(pModel) );
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Vec_IntPush( vBufs, Gia_ManBufNum(pNew) - Abc_NtkPoNum(pModel) );
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Vec_IntPush( vBufs, Abc_NtkPoNum(pModel) );
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}
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}
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}
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Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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{
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int fUseBufs = 1;
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int fUseInter = 0;
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Gia_Man_t * pNew, * pTemp;
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Abc_Ntk_t * pModel;
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Abc_Obj_t * pTerm;
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int i, Counter = -1;
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assert( Abc_NtkIsNetlist(pNtk) );
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// Abc_NtkPrintBoxInfo( pNtk );
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Abc_NtkFillTemp( pNtk );
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@@ -134,13 +147,14 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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pNew = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
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pNew->pName = Abc_UtilStrsav(pNtk->pName);
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pNew->pSpec = Abc_UtilStrsav(pNtk->pSpec);
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if ( fUseBufs )
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pNew->vBarBufs = Vec_IntAlloc( 1000 );
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// create PIs and buffers
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Abc_NtkForEachPi( pNtk, pTerm, i )
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pTerm->iTemp = Gia_ManAppendCi( pNew );
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Abc_NtkForEachPi( pNtk, pTerm, i )
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// Abc_ObjFanout0(pTerm)->iTemp = Gia_ManAppendBuf( pNew, pTerm->iTemp );
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Abc_ObjFanout0(pTerm)->iTemp = pTerm->iTemp;
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Abc_ObjFanout0(pTerm)->iTemp = fUseInter ? Gia_ManAppendBuf(pNew, pTerm->iTemp) : pTerm->iTemp;
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// create DFS order of nets
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if ( !pNtk->pDesign )
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@@ -151,7 +165,7 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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// call recursively
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Gia_ManHashAlloc( pNew );
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Gia_ManFlattenLogicHierarchy_rec( pNew, pNtk, &Counter );
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Gia_ManFlattenLogicHierarchy_rec( pNew, pNtk, &Counter, pNew->vBarBufs );
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Gia_ManHashStop( pNew );
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printf( "Hierarchy reader flattened %d instances of logic boxes.\n", Counter );
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@@ -164,11 +178,22 @@ Gia_Man_t * Gia_ManFlattenLogicHierarchy( Abc_Ntk_t * pNtk )
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// create buffers and POs
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Abc_NtkForEachPo( pNtk, pTerm, i )
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// pTerm->iTemp = Gia_ManAppendBuf( pNew, Abc_ObjFanin0(pTerm)->iTemp );
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pTerm->iTemp = Abc_ObjFanin0(pTerm)->iTemp;
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pTerm->iTemp = fUseInter ? Gia_ManAppendBuf(pNew, Abc_ObjFanin0(pTerm)->iTemp) : Abc_ObjFanin0(pTerm)->iTemp;
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Abc_NtkForEachPo( pNtk, pTerm, i )
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Gia_ManAppendCo( pNew, pTerm->iTemp );
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// save buffers
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if ( fUseInter )
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{
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Vec_IntPush( pNew->vBarBufs, 0 );
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Vec_IntPush( pNew->vBarBufs, Abc_NtkPiNum(pNtk) );
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Vec_IntPush( pNew->vBarBufs, Gia_ManBufNum(pNew) - Abc_NtkPoNum(pNtk) );
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Vec_IntPush( pNew->vBarBufs, Abc_NtkPoNum(pNtk) );
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}
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if ( fUseBufs )
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Vec_IntPrint( pNew->vBarBufs );
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// cleanup
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pNew = Gia_ManCleanup( pTemp = pNew );
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Gia_ManStop( pTemp );
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return pNew;
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