2013-07-17 23:19:33 +02:00
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/**CFile****************************************************************
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FileName [mpmGates.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Configurable technology mapper.]
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Synopsis [Standard-cell mapping.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 1, 2013.]
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Revision [$Id: mpmGates.c,v 1.00 2013/06/01 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "mpmInt.h"
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#include "misc/st/st.h"
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#include "map/mio/mio.h"
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#include "map/scl/sclInt.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Finds matches fore each DSD class.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Int_t * Mpm_ManFindDsdMatches( Mpm_Man_t * p, void * pScl, Vec_Int_t ** pvNpnCosts )
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{
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int fVerbose = p->pPars->fVeryVerbose;
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SC_Lib * pLib = (SC_Lib *)pScl;
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Vec_Int_t * vClasses;
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SC_Cell * pRepr;
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int i, Config, iClass;
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word Truth;
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vClasses = Vec_IntStartFull( 600 );
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*pvNpnCosts = Vec_IntStartFull( 600 );
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SC_LibForEachCellClass( pLib, pRepr, i )
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{
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if ( pRepr->n_inputs > 6 || pRepr->n_outputs > 1 )
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{
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if ( fVerbose )
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printf( "Skipping cell %s with %d inputs and %d outputs\n", pRepr->pName, pRepr->n_inputs, pRepr->n_outputs );
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continue;
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}
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Truth = *Vec_WrdArray( SC_CellPin(pRepr, pRepr->n_inputs)->vFunc );
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Config = Mpm_CutCheckDsd6( p, Truth );
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if ( Config == -1 )
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{
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if ( fVerbose )
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printf( "Skipping cell %s with non-DSD function\n", pRepr->pName );
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continue;
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}
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iClass = Config >> 17;
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Config = (pRepr->Id << 17) | (Config & 0x1FFFF);
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// write gate and NPN config for this DSD class
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Vec_IntWriteEntry( vClasses, iClass, Config );
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Vec_IntWriteEntry( *pvNpnCosts, iClass, (int)(100 * pRepr->area) );
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if ( !fVerbose )
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continue;
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printf( "Gate %5d %-30s : ", pRepr->Id, pRepr->pName );
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printf( "Class %3d ", iClass );
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printf( "Area %10.3f ", pRepr->area );
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2013-07-17 23:21:05 +02:00
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Extra_PrintBinary( stdout, (unsigned *)&Config, 17 );
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2013-07-17 23:19:33 +02:00
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printf( " " );
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Kit_DsdPrintFromTruth( (unsigned *)&Truth, pRepr->n_inputs ); printf( "\n" );
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}
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return vClasses;
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}
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/**Function*************************************************************
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Synopsis [Find mapping of DSD classes into Genlib library cells.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Mpm_ManFindCells( Mio_Library_t * pMio, SC_Lib * pScl, Vec_Int_t * vNpnGates )
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{
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Vec_Ptr_t * vNpnGatesMio;
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Mio_Gate_t * pMioGate;
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SC_Cell * pCell;
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int iCell, iClass;
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vNpnGatesMio = Vec_PtrStart( Vec_IntSize(vNpnGates) );
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Vec_IntForEachEntry( vNpnGates, iCell, iClass )
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{
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if ( iCell == -1 )
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continue;
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pCell = SC_LibCell( pScl, (iCell >> 17) );
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pMioGate = Mio_LibraryReadGateByName( pMio, pCell->pName, NULL );
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assert( pMioGate != NULL );
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Vec_PtrWriteEntry( vNpnGatesMio, iClass, pMioGate );
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}
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return vNpnGatesMio;
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}
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/**Function*************************************************************
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Synopsis [Derive mapped network as an ABC network.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Int_t * Mpm_ManFindMappedNodes( Mpm_Man_t * p )
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{
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Vec_Int_t * vNodes;
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Mig_Obj_t * pObj;
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vNodes = Vec_IntAlloc( 1000 );
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Mig_ManForEachObj( p->pMig, pObj )
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if ( Mig_ObjIsNode(pObj) && Mpm_ObjMapRef(p, pObj) )
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Vec_IntPush( vNodes, Mig_ObjId(pObj) );
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return vNodes;
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}
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Abc_Obj_t * Mpm_ManGetAbcNode( Abc_Ntk_t * pNtk, Vec_Int_t * vCopy, int iMigLit )
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{
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Abc_Obj_t * pObj;
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int iObjId = Vec_IntEntry( vCopy, iMigLit );
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if ( iObjId >= 0 )
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return Abc_NtkObj( pNtk, iObjId );
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iObjId = Vec_IntEntry( vCopy, Abc_LitNot(iMigLit) );
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assert( iObjId >= 0 );
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pObj = Abc_NtkCreateNodeInv( pNtk, Abc_NtkObj(pNtk, iObjId) );
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Vec_IntWriteEntry( vCopy, iMigLit, Abc_ObjId(pObj) );
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return pObj;
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}
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Abc_Ntk_t * Mpm_ManDeriveMappedAbcNtk( Mpm_Man_t * p, Mio_Library_t * pMio )
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{
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Abc_Ntk_t * pNtk;
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Vec_Ptr_t * vNpnGatesMio;
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Vec_Int_t * vNodes, * vCopy;
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Abc_Obj_t * pObj, * pFanin;
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Mig_Obj_t * pNode;
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Mpm_Cut_t * pCutBest;
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int i, k, iNode, iMigLit, fCompl;
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// find mapping of SCL cells into MIO cells
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vNpnGatesMio = Mpm_ManFindCells( pMio, (SC_Lib *)p->pPars->pScl, p->vGateNpnConfig );
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// create mapping for each phase of each node
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vCopy = Vec_IntStartFull( 2 * Mig_ManObjNum(p->pMig) );
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// get internal nodes
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vNodes = Mpm_ManFindMappedNodes( p );
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// start the network
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pNtk = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_MAP, 1 );
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pNtk->pName = Extra_UtilStrsav( p->pMig->pName );
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pNtk->pManFunc = pMio;
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// create primary inputs
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Mig_ManForEachCi( p->pMig, pNode, i )
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{
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pObj = Abc_NtkCreatePi(pNtk);
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Vec_IntWriteEntry( vCopy, Abc_Var2Lit( Mig_ObjId(pNode), 0 ), Abc_ObjId(pObj) );
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}
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Abc_NtkAddDummyPiNames( pNtk );
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// create constant nodes
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pObj = Abc_NtkCreateNodeConst0(pNtk);
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Vec_IntWriteEntry( vCopy, Abc_Var2Lit( 0, 0 ), Abc_ObjId(pObj) );
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pObj = Abc_NtkCreateNodeConst1(pNtk);
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Vec_IntWriteEntry( vCopy, Abc_Var2Lit( 0, 1 ), Abc_ObjId(pObj) );
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// create internal nodes
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Vec_IntForEachEntry( vNodes, iNode, i )
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{
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pNode = Mig_ManObj( p->pMig, iNode );
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pCutBest = Mpm_ObjCutBestP( p, pNode );
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pObj = Abc_NtkCreateNode( pNtk );
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pObj->pData = Vec_PtrEntry( vNpnGatesMio, Abc_Lit2Var(pCutBest->iFunc) );
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fCompl = Abc_LitIsCompl(pCutBest->iFunc);
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Mpm_CutForEachLeafLit( pCutBest, iMigLit, k )
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{
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pFanin = Mpm_ManGetAbcNode( pNtk, vCopy, iMigLit );
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Abc_ObjAddFanin( pObj, pFanin );
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}
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Vec_IntWriteEntry( vCopy, Abc_Var2Lit( iNode, fCompl ), Abc_ObjId(pObj) );
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}
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// create primary outputs
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Mig_ManForEachCo( p->pMig, pNode, i )
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{
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pObj = Abc_NtkCreatePo(pNtk);
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pFanin = Mpm_ManGetAbcNode( pNtk, vCopy, Mig_ObjFaninLit(pNode, 0) );
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Abc_ObjAddFanin( pObj, pFanin );
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}
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Abc_NtkAddDummyPoNames( pNtk );
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// clean up
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Vec_PtrFree( vNpnGatesMio );
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Vec_IntFree( vNodes );
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Vec_IntFree( vCopy );
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return pNtk;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_Ntk_t * Mpm_ManPerformCellMapping( Mig_Man_t * pMig, Mpm_Par_t * pPars, Mio_Library_t * pMio )
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{
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Abc_Ntk_t * pNew;
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Mpm_Man_t * p;
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assert( pPars->fMap4Gates );
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p = Mpm_ManStart( pMig, pPars );
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if ( p->pPars->fVerbose )
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Mpm_ManPrintStatsInit( p );
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p->vGateNpnConfig = Mpm_ManFindDsdMatches( p, p->pPars->pScl, &p->vNpnCosts );
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Mpm_ManPrepare( p );
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Mpm_ManPerform( p );
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if ( p->pPars->fVerbose )
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Mpm_ManPrintStats( p );
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pNew = Mpm_ManDeriveMappedAbcNtk( p, pMio );
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Mpm_ManStop( p );
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return pNew;
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}
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Abc_Ntk_t * Mpm_ManCellMapping( Gia_Man_t * pGia, Mpm_Par_t * pPars, void * pMio )
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{
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Mig_Man_t * p;
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Abc_Ntk_t * pNew;
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assert( pMio != NULL );
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assert( pPars->pLib->LutMax <= MPM_VAR_MAX );
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assert( pPars->nNumCuts <= MPM_CUT_MAX );
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if ( pPars->fUseGates )
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{
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pGia = Gia_ManDupMuxes( pGia );
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p = Mig_ManCreate( pGia );
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Gia_ManStop( pGia );
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}
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else
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p = Mig_ManCreate( pGia );
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pNew = Mpm_ManPerformCellMapping( p, pPars, (Mio_Library_t *)pMio );
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Mig_ManStop( p );
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return pNew;
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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