mirror of https://github.com/YosysHQ/abc.git
New technology mapper.
This commit is contained in:
Alan Mishchenko
parent
d22da3aec4
commit
10c90de054
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@ -2507,6 +2507,10 @@ SOURCE=.\src\map\mpm\mpmDsd.c
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# End Source File
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# Begin Source File
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SOURCE=.\src\map\mpm\mpmGates.c
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# End Source File
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# Begin Source File
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SOURCE=.\src\map\mpm\mpmInt.h
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# End Source File
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# Begin Source File
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@ -29528,15 +29528,17 @@ usage:
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***********************************************************************/
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int Abc_CommandAbc9If2( Abc_Frame_t * pAbc, int argc, char ** argv )
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{
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extern Gia_Man_t * Mpm_ManMappingTest( Gia_Man_t * p, Mpm_Par_t * pPars );
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extern Abc_Ntk_t * Mpm_ManCellMapping( Gia_Man_t * p, Mpm_Par_t * pPars, void * pMio );
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extern Gia_Man_t * Mpm_ManLutMapping( Gia_Man_t * p, Mpm_Par_t * pPars );
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char Buffer[200];
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Abc_Ntk_t * pTemp;
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Gia_Man_t * pNew;
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Mpm_Par_t Pars, * pPars = &Pars;
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int c, nLutSize = 6;
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// set defaults
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Mpm_ManSetParsDefault( pPars );
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "KCDtmzrcuvwh" ) ) != EOF )
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while ( ( c = Extra_UtilGetopt( argc, argv, "KCDtmzrcuxvwh" ) ) != EOF )
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{
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switch ( c )
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{
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@ -29596,6 +29598,9 @@ int Abc_CommandAbc9If2( Abc_Frame_t * pAbc, int argc, char ** argv )
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case 'u':
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pPars->fMap4Aig ^= 1;
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break;
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case 'x':
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pPars->fMap4Gates ^= 1;
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break;
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case 'v':
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pPars->fVerbose ^= 1;
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break;
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@ -29612,17 +29617,48 @@ int Abc_CommandAbc9If2( Abc_Frame_t * pAbc, int argc, char ** argv )
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if ( pPars->fMap4Cnf )
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pPars->fUseDsd = 1;
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if ( pPars->fCutMin )
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pPars->fUseTruth = 1;
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// pPars->fUseDsd = 1;
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// perform mapping
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pNew = Mpm_ManMappingTest( pAbc->pGia, pPars );
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Mpm_LibLutFree( pPars->pLib );
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if ( pNew == NULL )
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pPars->fUseDsd = 1;
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// pPars->fUseTruth = 1;
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if ( pPars->fMap4Gates )
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{
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Abc_Print( -1, "Abc_CommandAbc9If2(): Mapping of GIA has failed.\n" );
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return 1;
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pPars->fUseDsd = 1;
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if ( pAbc->pLibScl == NULL )
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{
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Abc_Print( -1, "There is no SCL library available.\n" );
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return 1;
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}
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pPars->pScl = pAbc->pLibScl;
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}
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if ( pPars->fUseDsd || pPars->fUseTruth )
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pPars->fDeriveLuts = 1;
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// perform mapping
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if ( pPars->fMap4Gates )
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{
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if ( Abc_FrameReadLibGen() == NULL )
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{
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Abc_Print( -1, "There is no GENLIB library available.\n" );
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return 1;
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}
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pTemp = Mpm_ManCellMapping( pAbc->pGia, pPars, Abc_FrameReadLibGen() );
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Mpm_LibLutFree( pPars->pLib );
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if ( pTemp == NULL )
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{
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Abc_Print( -1, "Abc_CommandAbc9If2(): Mapping into standard cells has failed.\n" );
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return 1;
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}
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Abc_FrameReplaceCurrentNetwork( pAbc, pTemp );
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}
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else
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{
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pNew = Mpm_ManLutMapping( pAbc->pGia, pPars );
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Mpm_LibLutFree( pPars->pLib );
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if ( pNew == NULL )
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{
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Abc_Print( -1, "Abc_CommandAbc9If2(): Mapping into LUTs has failed.\n" );
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return 1;
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}
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Abc_FrameUpdateGia( pAbc, pNew );
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}
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Abc_FrameUpdateGia( pAbc, pNew );
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return 0;
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usage:
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@ -29630,7 +29666,7 @@ usage:
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sprintf(Buffer, "best possible" );
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else
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sprintf(Buffer, "%d", pPars->DelayTarget );
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Abc_Print( -2, "usage: &if2 [-KCD num] [-tmzrcuvwh]\n" );
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Abc_Print( -2, "usage: &if2 [-KCD num] [-tmzrcuxvwh]\n" );
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Abc_Print( -2, "\t performs technology mapping of the network\n" );
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Abc_Print( -2, "\t-K num : sets the LUT size for the mapping [default = %d]\n", nLutSize );
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Abc_Print( -2, "\t-C num : the max number of priority cuts (0 < num < 2^12) [default = %d]\n", pPars->nNumCuts );
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@ -29641,6 +29677,7 @@ usage:
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Abc_Print( -2, "\t-r : toggles using one round of mapping [default = %s]\n", pPars->fOneRound? "yes": "no" );
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Abc_Print( -2, "\t-c : toggles mapping for CNF computation [default = %s]\n", pPars->fMap4Cnf? "yes": "no" );
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Abc_Print( -2, "\t-u : toggles mapping for AIG computation [default = %s]\n", pPars->fMap4Aig? "yes": "no" );
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Abc_Print( -2, "\t-x : toggles mapping for standard cells [default = %s]\n", pPars->fMap4Gates? "yes": "no" );
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Abc_Print( -2, "\t-v : toggles verbose output [default = %s]\n", pPars->fVerbose? "yes": "no" );
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Abc_Print( -2, "\t-w : toggles very verbose output [default = %s]\n", pPars->fVeryVerbose? "yes": "no" );
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Abc_Print( -2, "\t-h : prints the command usage\n");
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@ -1,6 +1,7 @@
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SRC += src/map/mpm/mpmAbc.c \
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src/map/mpm/mpmCore.c \
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src/map/mpm/mpmDsd.c \
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src/map/mpm/mpmGates.c \
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src/map/mpm/mpmLib.c \
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src/map/mpm/mpmMan.c \
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src/map/mpm/mpmMap.c \
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@ -57,6 +57,7 @@ typedef struct Mpm_Par_t_ Mpm_Par_t;
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struct Mpm_Par_t_
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{
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Mpm_LibLut_t * pLib;
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void * pScl;
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int nNumCuts;
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int DelayTarget;
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int fUseGates;
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@ -67,6 +68,7 @@ struct Mpm_Par_t_
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int fDeriveLuts;
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int fMap4Cnf;
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int fMap4Aig;
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int fMap4Gates;
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int fVerbose;
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int fVeryVerbose;
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};
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@ -56,6 +56,7 @@ void Mpm_ManSetParsDefault( Mpm_Par_t * p )
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p->fDeriveLuts = 0; // use truth tables to derive AIG structure
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p->fMap4Cnf = 0; // mapping for CNF
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p->fMap4Aig = 0; // mapping for AIG
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p->fMap4Gates = 0; // mapping for gates
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p->fVerbose = 0; // verbose output
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p->fVeryVerbose = 0; // verbose output
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}
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@ -71,13 +72,15 @@ void Mpm_ManSetParsDefault( Mpm_Par_t * p )
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SeeAlso []
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***********************************************************************/
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Gia_Man_t * Mpm_ManPerformTest( Mig_Man_t * pMig, Mpm_Par_t * pPars )
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Gia_Man_t * Mpm_ManPerformLutMapping( Mig_Man_t * pMig, Mpm_Par_t * pPars )
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{
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Gia_Man_t * pNew;
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Mpm_Man_t * p;
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p = Mpm_ManStart( pMig, pPars );
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if ( p->pPars->fVerbose )
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Mpm_ManPrintStatsInit( p );
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// if ( p->pPars->fMap4Gates )
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// p->vGateNpnConfig = Mpm_ManFindDsdMatches( p, p->pPars->pScl, &p->vNpnCosts );
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Mpm_ManPrepare( p );
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Mpm_ManPerform( p );
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if ( p->pPars->fVerbose )
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@ -86,7 +89,7 @@ Gia_Man_t * Mpm_ManPerformTest( Mig_Man_t * pMig, Mpm_Par_t * pPars )
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Mpm_ManStop( p );
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return pNew;
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}
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Gia_Man_t * Mpm_ManMappingTest( Gia_Man_t * pGia, Mpm_Par_t * pPars )
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Gia_Man_t * Mpm_ManLutMapping( Gia_Man_t * pGia, Mpm_Par_t * pPars )
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{
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Mig_Man_t * p;
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Gia_Man_t * pNew;
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@ -100,7 +103,7 @@ Gia_Man_t * Mpm_ManMappingTest( Gia_Man_t * pGia, Mpm_Par_t * pPars )
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}
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else
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p = Mig_ManCreate( pGia );
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pNew = Mpm_ManPerformTest( p, pPars );
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pNew = Mpm_ManPerformLutMapping( p, pPars );
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Mig_ManStop( p );
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return pNew;
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}
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@ -643,7 +643,6 @@ static Mpm_Dsd_t s_DsdClass6[595] = {
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void Mpm_ManPrintDsdStats( Mpm_Man_t * p )
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{
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int i, Absent = 0;
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for ( i = 0; i < 595; i++ )
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{
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if ( p->nCountDsd[i] == 0 )
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@ -659,9 +658,9 @@ void Mpm_ManPrintDsdStats( Mpm_Man_t * p )
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printf( "\n" );
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}
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}
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printf( "Unused classes = %d (%.2f %%). Non-DSD cuts = %d (%.2f %%).\n",
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Absent, 100.0 * Absent / 595,
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p->nNonDsd, 100.0 * p->nNonDsd / p->nCutsMergedAll );
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printf( "Unused classes = %d (%.2f %%). ", Absent, 100.0 * Absent / 595 );
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printf( "Non-DSD cuts = %d (%.2f %%). ", p->nNonDsd, 100.0 * p->nNonDsd / p->nCutsMergedAll );
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printf( "No-match cuts = %d (%.2f %%).\n", p->nNoMatch, 100.0 * p->nNoMatch / p->nCutsMergedAll );
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}
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/**Function*************************************************************
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@ -870,6 +869,31 @@ word Mpm_CutTruthFromDsd( Mpm_Man_t * pMan, Mpm_Cut_t * pCut, int iClass )
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return uTruth;
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}
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/**Function*************************************************************
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Synopsis [Checks hash table for DSD class.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Mpm_CutCheckDsd6( Mpm_Man_t * p, word t )
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{
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int fCompl, Entry, Config;
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if ( (fCompl = (t & 1)) )
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t = ~t;
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Entry = *Hsh_IntManLookup( p->pHash, (unsigned *)&t );
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if ( Entry == -1 )
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return -1;
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Config = Vec_IntEntry( p->vConfgRes, Entry );
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if ( fCompl )
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Config ^= (1 << 16);
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return Config;
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}
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/**Function*************************************************************
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Synopsis []
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@ -884,7 +908,7 @@ word Mpm_CutTruthFromDsd( Mpm_Man_t * pMan, Mpm_Cut_t * pCut, int iClass )
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int Mpm_CutComputeDsd6( Mpm_Man_t * p, Mpm_Cut_t * pCut, Mpm_Cut_t * pCut0, Mpm_Cut_t * pCut1, Mpm_Cut_t * pCutC, int fCompl0, int fCompl1, int fComplC, int Type )
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{
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int fVerbose = 0;
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int i, Config, iClass, Entry, fCompl = 0;
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int i, Config, iClass, fCompl;
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int pLeavesNew[6] = { -1, -1, -1, -1, -1, -1 };
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word t = 0;
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if ( pCutC == NULL )
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@ -946,23 +970,31 @@ Kit_DsdPrintFromTruth( (unsigned *)&t, 6 ); printf( "\n" );
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t = (tC & t1) | (~tC & t0);
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}
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if ( t & 1 )
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{
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fCompl = 1; t = ~t;
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}
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Entry = *Hsh_IntManLookup( p->pHash, (unsigned *)&t );
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if ( Entry == -1 )
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// find configuration
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Config = Mpm_CutCheckDsd6( p, t );
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if ( Config == -1 )
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{
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p->nNonDsd++;
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return 0;
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}
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Config = Vec_IntEntry( p->vConfgRes, Entry );
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if ( Config & (1 << 16) )
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fCompl ^= 1;
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// get the class
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iClass = Config >> 17;
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pCut->iFunc = Abc_Var2Lit( iClass, fCompl );
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fCompl = (Config >> 16) & 1;
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Config &= 0xFFFF;
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assert( (Config >> 6) < 720 );
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// check if the gate exists
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if ( p->pPars->fMap4Gates )
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{
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if ( Vec_IntEntry(p->vGateNpnConfig, iClass) < 0 )
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{
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p->nNoMatch++;
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return 0;
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}
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}
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// set the function
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pCut->iFunc = Abc_Var2Lit( iClass, fCompl );
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if ( fVerbose )
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{
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@ -971,11 +1003,13 @@ Mpm_CutPrint( pCut1 );
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Mpm_CutPrint( pCut );
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}
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// update cut
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assert( (Config >> 6) < 720 );
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for ( i = 0; i < (int)pCut->nLeaves; i++ )
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pLeavesNew[(int)p->Perm6[Config >> 6]] = Abc_LitNotCond( pCut->pLeaves[i], (Config >> i) & 1 );
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pLeavesNew[(int)(p->Perm6[Config >> 6][i])] = Abc_LitNotCond( pCut->pLeaves[i], (Config >> i) & 1 );
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pCut->nLeaves = p->pDsd6[iClass].nVars;
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// for ( i = 0; i < (int)pCut->nLeaves; i++ )
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// assert( pLeavesNew[i] != -1 );
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for ( i = 0; i < (int)pCut->nLeaves; i++ )
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assert( pLeavesNew[i] != -1 );
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for ( i = 0; i < (int)pCut->nLeaves; i++ )
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pCut->pLeaves[i] = pLeavesNew[i];
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p->nCountDsd[iClass]++;
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@ -0,0 +1,279 @@
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/**CFile****************************************************************
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FileName [mpmGates.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Configurable technology mapper.]
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Synopsis [Standard-cell mapping.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 1, 2013.]
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Revision [$Id: mpmGates.c,v 1.00 2013/06/01 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "mpmInt.h"
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#include "misc/st/st.h"
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#include "map/mio/mio.h"
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#include "map/scl/sclInt.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis [Finds matches fore each DSD class.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Int_t * Mpm_ManFindDsdMatches( Mpm_Man_t * p, void * pScl, Vec_Int_t ** pvNpnCosts )
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{
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int fVerbose = p->pPars->fVeryVerbose;
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SC_Lib * pLib = (SC_Lib *)pScl;
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Vec_Int_t * vClasses;
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SC_Cell * pRepr;
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int i, Config, iClass;
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word Truth;
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vClasses = Vec_IntStartFull( 600 );
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*pvNpnCosts = Vec_IntStartFull( 600 );
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SC_LibForEachCellClass( pLib, pRepr, i )
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{
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if ( pRepr->n_inputs > 6 || pRepr->n_outputs > 1 )
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{
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if ( fVerbose )
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printf( "Skipping cell %s with %d inputs and %d outputs\n", pRepr->pName, pRepr->n_inputs, pRepr->n_outputs );
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continue;
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}
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Truth = *Vec_WrdArray( SC_CellPin(pRepr, pRepr->n_inputs)->vFunc );
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Config = Mpm_CutCheckDsd6( p, Truth );
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if ( Config == -1 )
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{
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if ( fVerbose )
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printf( "Skipping cell %s with non-DSD function\n", pRepr->pName );
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continue;
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}
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iClass = Config >> 17;
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Config = (pRepr->Id << 17) | (Config & 0x1FFFF);
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// write gate and NPN config for this DSD class
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Vec_IntWriteEntry( vClasses, iClass, Config );
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Vec_IntWriteEntry( *pvNpnCosts, iClass, (int)(100 * pRepr->area) );
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if ( !fVerbose )
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continue;
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printf( "Gate %5d %-30s : ", pRepr->Id, pRepr->pName );
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printf( "Class %3d ", iClass );
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printf( "Area %10.3f ", pRepr->area );
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Extra_PrintBinary( stdout, &Config, 17 );
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printf( " " );
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Kit_DsdPrintFromTruth( (unsigned *)&Truth, pRepr->n_inputs ); printf( "\n" );
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}
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return vClasses;
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}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Find mapping of DSD classes into Genlib library cells.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Vec_Ptr_t * Mpm_ManFindCells( Mio_Library_t * pMio, SC_Lib * pScl, Vec_Int_t * vNpnGates )
|
||||
{
|
||||
Vec_Ptr_t * vNpnGatesMio;
|
||||
Mio_Gate_t * pMioGate;
|
||||
SC_Cell * pCell;
|
||||
int iCell, iClass;
|
||||
vNpnGatesMio = Vec_PtrStart( Vec_IntSize(vNpnGates) );
|
||||
Vec_IntForEachEntry( vNpnGates, iCell, iClass )
|
||||
{
|
||||
if ( iCell == -1 )
|
||||
continue;
|
||||
pCell = SC_LibCell( pScl, (iCell >> 17) );
|
||||
pMioGate = Mio_LibraryReadGateByName( pMio, pCell->pName, NULL );
|
||||
assert( pMioGate != NULL );
|
||||
Vec_PtrWriteEntry( vNpnGatesMio, iClass, pMioGate );
|
||||
}
|
||||
return vNpnGatesMio;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Derive mapped network as an ABC network.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Vec_Int_t * Mpm_ManFindMappedNodes( Mpm_Man_t * p )
|
||||
{
|
||||
Vec_Int_t * vNodes;
|
||||
Mig_Obj_t * pObj;
|
||||
vNodes = Vec_IntAlloc( 1000 );
|
||||
Mig_ManForEachObj( p->pMig, pObj )
|
||||
if ( Mig_ObjIsNode(pObj) && Mpm_ObjMapRef(p, pObj) )
|
||||
Vec_IntPush( vNodes, Mig_ObjId(pObj) );
|
||||
return vNodes;
|
||||
}
|
||||
Abc_Obj_t * Mpm_ManGetAbcNode( Abc_Ntk_t * pNtk, Vec_Int_t * vCopy, int iMigLit )
|
||||
{
|
||||
Abc_Obj_t * pObj;
|
||||
int iObjId = Vec_IntEntry( vCopy, iMigLit );
|
||||
if ( iObjId >= 0 )
|
||||
return Abc_NtkObj( pNtk, iObjId );
|
||||
iObjId = Vec_IntEntry( vCopy, Abc_LitNot(iMigLit) );
|
||||
assert( iObjId >= 0 );
|
||||
pObj = Abc_NtkCreateNodeInv( pNtk, Abc_NtkObj(pNtk, iObjId) );
|
||||
Vec_IntWriteEntry( vCopy, iMigLit, Abc_ObjId(pObj) );
|
||||
return pObj;
|
||||
}
|
||||
Abc_Ntk_t * Mpm_ManDeriveMappedAbcNtk( Mpm_Man_t * p, Mio_Library_t * pMio )
|
||||
{
|
||||
Abc_Ntk_t * pNtk;
|
||||
Vec_Ptr_t * vNpnGatesMio;
|
||||
Vec_Int_t * vNodes, * vCopy;
|
||||
Abc_Obj_t * pObj, * pFanin;
|
||||
Mig_Obj_t * pNode;
|
||||
Mpm_Cut_t * pCutBest;
|
||||
int i, k, iNode, iMigLit, fCompl;
|
||||
|
||||
// find mapping of SCL cells into MIO cells
|
||||
vNpnGatesMio = Mpm_ManFindCells( pMio, (SC_Lib *)p->pPars->pScl, p->vGateNpnConfig );
|
||||
|
||||
// create mapping for each phase of each node
|
||||
vCopy = Vec_IntStartFull( 2 * Mig_ManObjNum(p->pMig) );
|
||||
|
||||
// get internal nodes
|
||||
vNodes = Mpm_ManFindMappedNodes( p );
|
||||
|
||||
// start the network
|
||||
pNtk = Abc_NtkAlloc( ABC_NTK_LOGIC, ABC_FUNC_MAP, 1 );
|
||||
pNtk->pName = Extra_UtilStrsav( p->pMig->pName );
|
||||
pNtk->pManFunc = pMio;
|
||||
|
||||
// create primary inputs
|
||||
Mig_ManForEachCi( p->pMig, pNode, i )
|
||||
{
|
||||
pObj = Abc_NtkCreatePi(pNtk);
|
||||
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( Mig_ObjId(pNode), 0 ), Abc_ObjId(pObj) );
|
||||
}
|
||||
Abc_NtkAddDummyPiNames( pNtk );
|
||||
|
||||
// create constant nodes
|
||||
pObj = Abc_NtkCreateNodeConst0(pNtk);
|
||||
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( 0, 0 ), Abc_ObjId(pObj) );
|
||||
pObj = Abc_NtkCreateNodeConst1(pNtk);
|
||||
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( 0, 1 ), Abc_ObjId(pObj) );
|
||||
|
||||
// create internal nodes
|
||||
Vec_IntForEachEntry( vNodes, iNode, i )
|
||||
{
|
||||
pNode = Mig_ManObj( p->pMig, iNode );
|
||||
pCutBest = Mpm_ObjCutBestP( p, pNode );
|
||||
pObj = Abc_NtkCreateNode( pNtk );
|
||||
pObj->pData = Vec_PtrEntry( vNpnGatesMio, Abc_Lit2Var(pCutBest->iFunc) );
|
||||
fCompl = Abc_LitIsCompl(pCutBest->iFunc);
|
||||
Mpm_CutForEachLeafLit( pCutBest, iMigLit, k )
|
||||
{
|
||||
pFanin = Mpm_ManGetAbcNode( pNtk, vCopy, iMigLit );
|
||||
Abc_ObjAddFanin( pObj, pFanin );
|
||||
}
|
||||
Vec_IntWriteEntry( vCopy, Abc_Var2Lit( iNode, fCompl ), Abc_ObjId(pObj) );
|
||||
}
|
||||
|
||||
// create primary outputs
|
||||
Mig_ManForEachCo( p->pMig, pNode, i )
|
||||
{
|
||||
pObj = Abc_NtkCreatePo(pNtk);
|
||||
pFanin = Mpm_ManGetAbcNode( pNtk, vCopy, Mig_ObjFaninLit(pNode, 0) );
|
||||
Abc_ObjAddFanin( pObj, pFanin );
|
||||
}
|
||||
Abc_NtkAddDummyPoNames( pNtk );
|
||||
|
||||
// clean up
|
||||
Vec_PtrFree( vNpnGatesMio );
|
||||
Vec_IntFree( vNodes );
|
||||
Vec_IntFree( vCopy );
|
||||
return pNtk;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Mpm_ManPerformCellMapping( Mig_Man_t * pMig, Mpm_Par_t * pPars, Mio_Library_t * pMio )
|
||||
{
|
||||
Abc_Ntk_t * pNew;
|
||||
Mpm_Man_t * p;
|
||||
assert( pPars->fMap4Gates );
|
||||
p = Mpm_ManStart( pMig, pPars );
|
||||
if ( p->pPars->fVerbose )
|
||||
Mpm_ManPrintStatsInit( p );
|
||||
p->vGateNpnConfig = Mpm_ManFindDsdMatches( p, p->pPars->pScl, &p->vNpnCosts );
|
||||
Mpm_ManPrepare( p );
|
||||
Mpm_ManPerform( p );
|
||||
if ( p->pPars->fVerbose )
|
||||
Mpm_ManPrintStats( p );
|
||||
pNew = Mpm_ManDeriveMappedAbcNtk( p, pMio );
|
||||
Mpm_ManStop( p );
|
||||
return pNew;
|
||||
}
|
||||
Abc_Ntk_t * Mpm_ManCellMapping( Gia_Man_t * pGia, Mpm_Par_t * pPars, void * pMio )
|
||||
{
|
||||
Mig_Man_t * p;
|
||||
Abc_Ntk_t * pNew;
|
||||
assert( pMio != NULL );
|
||||
assert( pPars->pLib->LutMax <= MPM_VAR_MAX );
|
||||
assert( pPars->nNumCuts <= MPM_CUT_MAX );
|
||||
if ( pPars->fUseGates )
|
||||
{
|
||||
pGia = Gia_ManDupMuxes( pGia );
|
||||
p = Mig_ManCreate( pGia );
|
||||
Gia_ManStop( pGia );
|
||||
}
|
||||
else
|
||||
p = Mig_ManCreate( pGia );
|
||||
pNew = Mpm_ManPerformCellMapping( p, pPars, (Mio_Library_t *)pMio );
|
||||
Mig_ManStop( p );
|
||||
return pNew;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
ABC_NAMESPACE_IMPL_END
|
||||
|
||||
|
|
@ -101,10 +101,10 @@ struct Mpm_Man_t_
|
|||
int nTruWords; // words in the truth table
|
||||
Mpm_LibLut_t * pLibLut; // LUT library
|
||||
// mapping attributes
|
||||
int GloRequired; // global arrival time
|
||||
int GloArea; // total area
|
||||
int GloEdge; // total edge
|
||||
int fMainRun; // after preprocessing is finished
|
||||
int GloRequired; // global arrival time
|
||||
word GloArea; // total area
|
||||
word GloEdge; // total edge
|
||||
// cut management
|
||||
Mmr_Step_t * pManCuts; // cut memory
|
||||
// temporary cut storage
|
||||
|
|
@ -140,6 +140,8 @@ struct Mpm_Man_t_
|
|||
Vec_Int_t * vMap2Perm; // maps number into its permutation
|
||||
unsigned uPermMask[3];
|
||||
unsigned uComplMask[3];
|
||||
Vec_Int_t * vGateNpnConfig;
|
||||
Vec_Int_t * vNpnCosts; // area cost of each NPN class
|
||||
// mapping attributes
|
||||
Vec_Int_t vCutBests; // cut best
|
||||
Vec_Int_t vCutLists; // cut list
|
||||
|
|
@ -152,6 +154,7 @@ struct Mpm_Man_t_
|
|||
Vec_Int_t vEdges; // edge
|
||||
int nCountDsd[600];
|
||||
int nNonDsd;
|
||||
int nNoMatch;
|
||||
// statistics
|
||||
int nCutsMerged;
|
||||
int nCutsMergedAll;
|
||||
|
|
@ -218,6 +221,8 @@ static inline void Mpm_VarsSwap( int * V2P, int * P2V, int iVar, int jVar
|
|||
// iterators over cut leaves
|
||||
#define Mpm_CutForEachLeafId( pCut, iLeafId, i ) \
|
||||
for ( i = 0; i < (int)pCut->nLeaves && ((iLeafId = Abc_Lit2Var(pCut->pLeaves[i])), 1); i++ )
|
||||
#define Mpm_CutForEachLeafLit( pCut, iLeafLit, i ) \
|
||||
for ( i = 0; i < (int)pCut->nLeaves && ((iLeafLit = pCut->pLeaves[i]), 1); i++ )
|
||||
#define Mpm_CutForEachLeaf( p, pCut, pLeaf, i ) \
|
||||
for ( i = 0; i < (int)pCut->nLeaves && (pLeaf = Mig_ManObj(p, Abc_Lit2Var(pCut->pLeaves[i]))); i++ )
|
||||
|
||||
|
|
@ -238,7 +243,10 @@ extern void Mpm_ManPrintDsdStats( Mpm_Man_t * p );
|
|||
extern void Mpm_ManPrintPerm( unsigned s );
|
||||
extern void Mpm_ManPrecomputePerms( Mpm_Man_t * p );
|
||||
extern word Mpm_CutTruthFromDsd( Mpm_Man_t * pMan, Mpm_Cut_t * pCut, int iDsdLit );
|
||||
extern int Mpm_CutCheckDsd6( Mpm_Man_t * p, word t );
|
||||
extern int Mpm_CutComputeDsd6( Mpm_Man_t * p, Mpm_Cut_t * pCut, Mpm_Cut_t * pCut0, Mpm_Cut_t * pCut1, Mpm_Cut_t * pCutC, int fCompl0, int fCompl1, int fComplC, int Type );
|
||||
/*=== mpmGates.c ===========================================================*/
|
||||
extern Vec_Int_t * Mpm_ManFindDsdMatches( Mpm_Man_t * p, void * pScl, Vec_Int_t ** pvNpnCosts );
|
||||
/*=== mpmLib.c ===========================================================*/
|
||||
extern Mpm_LibLut_t * Mpm_LibLutSetSimple( int nLutSize );
|
||||
extern void Mpm_LibLutFree( Mpm_LibLut_t * pLib );
|
||||
|
|
|
|||
|
|
@ -138,6 +138,8 @@ void Mpm_ManStop( Mpm_Man_t * p )
|
|||
Vec_IntFree( p->pHash->vData );
|
||||
Hsh_IntManStop( p->pHash );
|
||||
}
|
||||
Vec_IntFreeP( &p->vNpnCosts );
|
||||
Vec_IntFreeP( &p->vGateNpnConfig );
|
||||
Vec_PtrFree( p->vTemp );
|
||||
Mmr_StepStop( p->pManCuts );
|
||||
ABC_FREE( p->vObjPresUsed.pArray );
|
||||
|
|
|
|||
|
|
@ -158,6 +158,8 @@ static inline int Mpm_CutGetArea( Mpm_Man_t * p, Mpm_Cut_t * pCut )
|
|||
return MPM_UNIT_AREA * p->pDsd6[Abc_Lit2Var(pCut->iFunc)].nClauses;
|
||||
if ( p->pPars->fMap4Aig )
|
||||
return MPM_UNIT_AREA * p->pDsd6[Abc_Lit2Var(pCut->iFunc)].nAnds;
|
||||
if ( p->pPars->fMap4Gates )
|
||||
return MPM_UNIT_AREA * Vec_IntEntry( p->vNpnCosts, Abc_Lit2Var(pCut->iFunc) );
|
||||
return p->pLibLut->pLutAreas[pCut->nLeaves];
|
||||
}
|
||||
static inline word Mpm_CutGetSign( Mpm_Cut_t * pCut )
|
||||
|
|
|
|||
Loading…
Reference in New Issue