2005-11-14 17:01:00 +01:00
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/**CFile****************************************************************
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FileName [seqInt.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Construction and manipulation of sequential AIGs.]
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2005-11-20 17:01:00 +01:00
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Synopsis [Internal declarations.]
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2005-11-14 17:01:00 +01:00
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: seqInt.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef __SEQ_INT_H__
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#define __SEQ_INT_H__
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////////////////////////////////////////////////////////////////////////
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/// INCLUDES ///
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////////////////////////////////////////////////////////////////////////
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#include "abc.h"
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#include "cut.h"
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#include "main.h"
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#include "mio.h"
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#include "mapper.h"
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#include "fpga.h"
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2005-11-14 17:01:00 +01:00
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#include "seq.h"
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////////////////////////////////////////////////////////////////////////
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/// PARAMETERS ///
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////////////////////////////////////////////////////////////////////////
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#define SEQ_FULL_MASK 0xFFFFFFFF
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// node status after updating its arrival time
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enum { SEQ_UPDATE_FAIL, SEQ_UPDATE_NO, SEQ_UPDATE_YES };
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2005-11-14 17:01:00 +01:00
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////////////////////////////////////////////////////////////////////////
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/// BASIC TYPES ///
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////////////////////////////////////////////////////////////////////////
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// manager of sequential AIG
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struct Abc_Seq_t_
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{
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// sequential information
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Abc_Ntk_t * pNtk; // the network
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int nSize; // the number of entries in all internal arrays
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Vec_Int_t * vNums; // the number of latches on each edge in the AIG
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Vec_Ptr_t * vInits; // the initial states for each edge in the AIG
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Extra_MmFixed_t * pMmInits; // memory manager for latch structures used to remember init states
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int fVerbose; // the verbose flag
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float fEpsilon; // the accuracy for delay computation
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int fStandCells; // the flag denoting standard cell mapping
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int nMaxIters; // the max number of iterations
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int FiBestInt; // the best clock period
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float FiBestFloat; // the best clock period
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// K-feasible cuts
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int nVarsMax; // the max cut size
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Cut_Man_t * pCutMan; // cut manager
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Map_SuperLib_t * pSuperLib; // the current supergate library
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// sequential arrival time computation
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Vec_Int_t * vAFlows; // the area flow of each cut
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Vec_Int_t * vLValues; // the arrival times (L-Values of nodes)
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Vec_Int_t * vLValuesN; // the arrival times (L-Values of nodes)
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Vec_Str_t * vLags; // the lags of the mapped nodes
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Vec_Str_t * vLagsN; // the lags of the mapped nodes
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Vec_Str_t * vUses; // the phase usage
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// representation of the mapping
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Vec_Ptr_t * vMapAnds; // nodes visible in the mapping
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Vec_Vec_t * vMapCuts; // best cuts for each node
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Vec_Vec_t * vMapDelays; // the delay of each fanin
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Vec_Vec_t * vMapFanins; // the delay of each fanin
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// runtime stats
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int timeCuts; // runtime to compute the cuts
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int timeDelay; // runtime to compute the L-values
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int timeRet; // runtime to retime the resulting network
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int timeNtk; // runtime to create the final network
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};
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// data structure to store initial state
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typedef struct Seq_Lat_t_ Seq_Lat_t;
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struct Seq_Lat_t_
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{
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Seq_Lat_t * pNext; // the next Lat in the ring
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Seq_Lat_t * pPrev; // the prev Lat in the ring
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Abc_Obj_t * pLatch; // the real latch corresponding to Lat
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};
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// representation of latch on the edge
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typedef struct Seq_RetEdge_t_ Seq_RetEdge_t;
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struct Seq_RetEdge_t_ // 1 word
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{
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unsigned iNode : 24; // the ID of the node
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unsigned iEdge : 1; // the edge of the node
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unsigned iLatch : 7; // the latch number counting from the node
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};
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// representation of one retiming step
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typedef struct Seq_RetStep_t_ Seq_RetStep_t;
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struct Seq_RetStep_t_ // 1 word
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{
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unsigned iNode : 24; // the ID of the node
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unsigned nLatches : 8; // the number of latches to retime
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};
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// representation of one mapping match
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typedef struct Seq_Match_t_ Seq_Match_t;
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struct Seq_Match_t_ // 3 words
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{
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Abc_Obj_t * pAnd; // the AND gate used in the mapping
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Cut_Cut_t * pCut; // the cut used to map it
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Map_Super_t * pSuper; // the supergate used to implement the cut
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unsigned fCompl : 1; // the polarity of the AND gate
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unsigned fCutInv : 1; // the polarity of the cut
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unsigned PolUse : 2; // the polarity use of this node
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unsigned uPhase : 14; // the phase assignment at the boundary
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unsigned uPhaseR : 14; // the real phase assignment at the boundary
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};
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////////////////////////////////////////////////////////////////////////
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/// MACRO DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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// transforming retedges into ints and back
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static inline int Seq_RetEdge2Int( Seq_RetEdge_t Val ) { return *((int *)&Val); }
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static inline Seq_RetEdge_t Seq_Int2RetEdge( int Num ) { return *((Seq_RetEdge_t *)&Num); }
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// transforming retsteps into ints and back
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static inline int Seq_RetStep2Int( Seq_RetStep_t Val ) { return *((int *)&Val); }
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static inline Seq_RetStep_t Seq_Int2RetStep( int Num ) { return *((Seq_RetStep_t *)&Num); }
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// manipulating the number of latches on each edge
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static inline Vec_Int_t * Seq_ObjLNums( Abc_Obj_t * pObj ) { return ((Abc_Seq_t*)pObj->pNtk->pManFunc)->vNums; }
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static inline int Seq_ObjFaninL( Abc_Obj_t * pObj, int i ) { return Vec_IntEntry(Seq_ObjLNums(pObj), 2*pObj->Id + i); }
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static inline int Seq_ObjFaninL0( Abc_Obj_t * pObj ) { return Vec_IntEntry(Seq_ObjLNums(pObj), 2*pObj->Id + 0); }
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static inline int Seq_ObjFaninL1( Abc_Obj_t * pObj ) { return Vec_IntEntry(Seq_ObjLNums(pObj), 2*pObj->Id + 1); }
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static inline void Seq_ObjSetFaninL( Abc_Obj_t * pObj, int i, int nLats ) { Vec_IntWriteEntry(Seq_ObjLNums(pObj), 2*pObj->Id + i, nLats); }
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static inline void Seq_ObjSetFaninL0( Abc_Obj_t * pObj, int nLats ) { Vec_IntWriteEntry(Seq_ObjLNums(pObj), 2*pObj->Id + 0, nLats); }
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static inline void Seq_ObjSetFaninL1( Abc_Obj_t * pObj, int nLats ) { Vec_IntWriteEntry(Seq_ObjLNums(pObj), 2*pObj->Id + 1, nLats); }
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static inline void Seq_ObjAddFaninL( Abc_Obj_t * pObj, int i, int nLats ) { Vec_IntAddToEntry(Seq_ObjLNums(pObj), 2*pObj->Id + i, nLats); }
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static inline void Seq_ObjAddFaninL0( Abc_Obj_t * pObj, int nLats ) { Vec_IntAddToEntry(Seq_ObjLNums(pObj), 2*pObj->Id + 0, nLats); }
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static inline void Seq_ObjAddFaninL1( Abc_Obj_t * pObj, int nLats ) { Vec_IntAddToEntry(Seq_ObjLNums(pObj), 2*pObj->Id + 1, nLats); }
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static inline int Seq_ObjFanoutL( Abc_Obj_t * pObj, Abc_Obj_t * pFanout ) { return Seq_ObjFaninL( pFanout, Abc_ObjFanoutEdgeNum(pObj,pFanout) ); }
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static inline void Seq_ObjSetFanoutL( Abc_Obj_t * pObj, Abc_Obj_t * pFanout, int nLats ) { Seq_ObjSetFaninL( pFanout, Abc_ObjFanoutEdgeNum(pObj,pFanout), nLats ); }
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static inline void Seq_ObjAddFanoutL( Abc_Obj_t * pObj, Abc_Obj_t * pFanout, int nLats ) { Seq_ObjAddFaninL( pFanout, Abc_ObjFanoutEdgeNum(pObj,pFanout), nLats ); }
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static inline int Seq_ObjFaninLMin( Abc_Obj_t * pObj ) { assert( Abc_ObjIsNode(pObj) ); return ABC_MIN( Seq_ObjFaninL0(pObj), Seq_ObjFaninL1(pObj) ); }
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static inline int Seq_ObjFaninLMax( Abc_Obj_t * pObj ) { assert( Abc_ObjIsNode(pObj) ); return ABC_MAX( Seq_ObjFaninL0(pObj), Seq_ObjFaninL1(pObj) ); }
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// reading l-values and lags
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static inline Vec_Int_t * Seq_NodeLValues( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vLValues; }
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static inline Vec_Int_t * Seq_NodeLValuesN( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vLValuesN; }
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static inline int Seq_NodeGetLValue( Abc_Obj_t * pNode ) { return Vec_IntEntry( Seq_NodeLValues(pNode), (pNode)->Id ); }
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static inline void Seq_NodeSetLValue( Abc_Obj_t * pNode, int Value ) { Vec_IntWriteEntry( Seq_NodeLValues(pNode), (pNode)->Id, Value ); }
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static inline float Seq_NodeGetLValueP( Abc_Obj_t * pNode ) { return Abc_Int2Float( Vec_IntEntry( Seq_NodeLValues(pNode), (pNode)->Id ) ); }
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static inline float Seq_NodeGetLValueN( Abc_Obj_t * pNode ) { return Abc_Int2Float( Vec_IntEntry( Seq_NodeLValuesN(pNode), (pNode)->Id ) ); }
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static inline void Seq_NodeSetLValueP( Abc_Obj_t * pNode, float Value ) { Vec_IntWriteEntry( Seq_NodeLValues(pNode), (pNode)->Id, Abc_Float2Int(Value) ); }
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static inline void Seq_NodeSetLValueN( Abc_Obj_t * pNode, float Value ) { Vec_IntWriteEntry( Seq_NodeLValuesN(pNode), (pNode)->Id, Abc_Float2Int(Value) ); }
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2005-11-28 17:01:00 +01:00
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// reading area flows
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static inline Vec_Int_t * Seq_NodeFlow( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vAFlows; }
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static inline float Seq_NodeGetFlow( Abc_Obj_t * pNode ) { return Abc_Int2Float( Vec_IntEntry( Seq_NodeFlow(pNode), (pNode)->Id ) ); }
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static inline void Seq_NodeSetFlow( Abc_Obj_t * pNode, float Value ) { Vec_IntWriteEntry( Seq_NodeFlow(pNode), (pNode)->Id, Abc_Float2Int(Value) ); }
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// reading the contents of the lat
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static inline Abc_InitType_t Seq_LatInit( Seq_Lat_t * pLat ) { return ((unsigned)pLat->pPrev) & 3; }
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static inline Seq_Lat_t * Seq_LatNext( Seq_Lat_t * pLat ) { return pLat->pNext; }
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static inline Seq_Lat_t * Seq_LatPrev( Seq_Lat_t * pLat ) { return (void *)(((unsigned)pLat->pPrev) & (SEQ_FULL_MASK << 2)); }
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// setting the contents of the lat
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static inline void Seq_LatSetInit( Seq_Lat_t * pLat, Abc_InitType_t Init ) { pLat->pPrev = (void *)( (3 & Init) | (((unsigned)pLat->pPrev) & (SEQ_FULL_MASK << 2)) ); }
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static inline void Seq_LatSetNext( Seq_Lat_t * pLat, Seq_Lat_t * pNext ) { pLat->pNext = pNext; }
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static inline void Seq_LatSetPrev( Seq_Lat_t * pLat, Seq_Lat_t * pPrev ) { Abc_InitType_t Init = Seq_LatInit(pLat); pLat->pPrev = pPrev; Seq_LatSetInit(pLat, Init); }
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// accessing retiming lags
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static inline Cut_Man_t * Seq_NodeCutMan( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->pCutMan; }
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static inline Vec_Str_t * Seq_NodeLags( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vLags; }
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static inline Vec_Str_t * Seq_NodeLagsN( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vLagsN; }
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static inline char Seq_NodeGetLag( Abc_Obj_t * pNode ) { return Vec_StrEntry( Seq_NodeLags(pNode), (pNode)->Id ); }
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static inline char Seq_NodeGetLagN( Abc_Obj_t * pNode ) { return Vec_StrEntry( Seq_NodeLagsN(pNode), (pNode)->Id ); }
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static inline void Seq_NodeSetLag( Abc_Obj_t * pNode, char Value ) { Vec_StrWriteEntry( Seq_NodeLags(pNode), (pNode)->Id, (Value) ); }
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static inline void Seq_NodeSetLagN( Abc_Obj_t * pNode, char Value ) { Vec_StrWriteEntry( Seq_NodeLagsN(pNode), (pNode)->Id, (Value) ); }
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static inline int Seq_NodeComputeLag( int LValue, int Fi ) { return (LValue + 1024*Fi)/Fi - 1024 - (int)(LValue % Fi == 0); }
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static inline int Seq_NodeComputeLagFloat( float LValue, float Fi ) { return ((int)ceil(LValue/Fi)) - 1; }
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// phase usage
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static inline Vec_Str_t * Seq_NodeUses( Abc_Obj_t * pNode ) { return ((Abc_Seq_t *)(pNode)->pNtk->pManFunc)->vUses; }
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static inline char Seq_NodeGetUses( Abc_Obj_t * pNode ) { return Vec_StrEntry( Seq_NodeUses(pNode), (pNode)->Id ); }
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static inline void Seq_NodeSetUses( Abc_Obj_t * pNode, char Value ) { Vec_StrWriteEntry( Seq_NodeUses(pNode), (pNode)->Id, (Value) ); }
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// accessing initial states
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static inline Vec_Ptr_t * Seq_NodeLats( Abc_Obj_t * pObj ) { return ((Abc_Seq_t*)pObj->pNtk->pManFunc)->vInits; }
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static inline Seq_Lat_t * Seq_NodeGetRing( Abc_Obj_t * pObj, int Edge ) { return Vec_PtrEntry( Seq_NodeLats(pObj), (pObj->Id<<1)+Edge ); }
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static inline void Seq_NodeSetRing( Abc_Obj_t * pObj, int Edge, Seq_Lat_t * pLat ) { Vec_PtrWriteEntry( Seq_NodeLats(pObj), (pObj->Id<<1)+Edge, pLat ); }
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static inline Seq_Lat_t * Seq_NodeCreateLat( Abc_Obj_t * pObj ) { Seq_Lat_t * p = (Seq_Lat_t *)Extra_MmFixedEntryFetch( ((Abc_Seq_t*)pObj->pNtk->pManFunc)->pMmInits ); p->pNext = p->pPrev = NULL; p->pLatch = NULL; return p; }
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static inline void Seq_NodeRecycleLat( Abc_Obj_t * pObj, Seq_Lat_t * pLat ) { Extra_MmFixedEntryRecycle( ((Abc_Seq_t*)pObj->pNtk->pManFunc)->pMmInits, (char *)pLat ); }
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// getting hold of the structure storing initial states of the latches
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static inline Seq_Lat_t * Seq_NodeGetLatFirst( Abc_Obj_t * pObj, int Edge ) { return Seq_NodeGetRing(pObj, Edge); }
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static inline Seq_Lat_t * Seq_NodeGetLatLast( Abc_Obj_t * pObj, int Edge ) { return Seq_LatPrev( Seq_NodeGetRing(pObj, Edge) ); }
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static inline Seq_Lat_t * Seq_NodeGetLat( Abc_Obj_t * pObj, int Edge, int iLat ) { int c; Seq_Lat_t * pLat = Seq_NodeGetRing(pObj, Edge); for ( c = 0; c != iLat; c++ ) pLat = pLat->pNext; return pLat; }
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2005-11-27 17:01:00 +01:00
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static inline int Seq_NodeCountLats( Abc_Obj_t * pObj, int Edge ) { int c; Seq_Lat_t * pLat, * pRing = Seq_NodeGetRing(pObj, Edge); if ( pRing == NULL ) return 0; for ( c = 0, pLat = pRing; !c || pLat != pRing; c++ ) pLat = pLat->pNext; return c; }
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static inline void Seq_NodeCleanLats( Abc_Obj_t * pObj, int Edge ) { int c; Seq_Lat_t * pLat, * pRing = Seq_NodeGetRing(pObj, Edge); if ( pRing == NULL ) return ; for ( c = 0, pLat = pRing; !c || pLat != pRing; c++ ) pLat->pLatch = NULL, pLat = pLat->pNext; return; }
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2005-11-14 17:01:00 +01:00
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// getting/setting initial states of the latches
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static inline Abc_InitType_t Seq_NodeGetInitOne( Abc_Obj_t * pObj, int Edge, int iLat ) { return Seq_LatInit( Seq_NodeGetLat(pObj, Edge, iLat) ); }
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static inline Abc_InitType_t Seq_NodeGetInitFirst( Abc_Obj_t * pObj, int Edge ) { return Seq_LatInit( Seq_NodeGetLatFirst(pObj, Edge) ); }
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static inline Abc_InitType_t Seq_NodeGetInitLast( Abc_Obj_t * pObj, int Edge ) { return Seq_LatInit( Seq_NodeGetLatLast(pObj, Edge) ); }
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static inline void Seq_NodeSetInitOne( Abc_Obj_t * pObj, int Edge, int iLat, Abc_InitType_t Init ) { Seq_LatSetInit( Seq_NodeGetLat(pObj, Edge, iLat), Init ); }
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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2005-11-26 17:01:00 +01:00
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/*=== seqAigIter.c =============================================================*/
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2005-11-30 17:01:00 +01:00
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extern int Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
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2005-11-26 17:01:00 +01:00
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extern int Seq_NtkImplementRetiming( Abc_Ntk_t * pNtk, Vec_Str_t * vLags, int fVerbose );
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/*=== seqFpgaIter.c ============================================================*/
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2005-11-30 17:01:00 +01:00
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extern int Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose );
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2005-11-26 17:01:00 +01:00
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extern int Seq_FpgaNodeUpdateLValue( Abc_Obj_t * pObj, int Fi );
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/*=== seqMapIter.c ============================================================*/
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2005-11-30 17:01:00 +01:00
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extern int Seq_MapRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
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2005-11-26 17:01:00 +01:00
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/*=== seqRetIter.c =============================================================*/
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2005-11-30 17:01:00 +01:00
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extern int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose );
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2005-11-14 17:01:00 +01:00
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/*=== seqLatch.c ===============================================================*/
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extern void Seq_NodeInsertFirst( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init );
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extern void Seq_NodeInsertLast( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init );
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extern Abc_InitType_t Seq_NodeDeleteFirst( Abc_Obj_t * pObj, int Edge );
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extern Abc_InitType_t Seq_NodeDeleteLast( Abc_Obj_t * pObj, int Edge );
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/*=== seqUtil.c ================================================================*/
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2005-11-26 17:01:00 +01:00
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extern int Seq_NtkLevelMax( Abc_Ntk_t * pNtk );
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2005-11-14 17:01:00 +01:00
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extern int Seq_ObjFanoutLMax( Abc_Obj_t * pObj );
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extern int Seq_ObjFanoutLMin( Abc_Obj_t * pObj );
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extern int Seq_ObjFanoutLSum( Abc_Obj_t * pObj );
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extern int Seq_ObjFaninLSum( Abc_Obj_t * pObj );
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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#endif
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