mirror of https://github.com/YosysHQ/abc.git
Version abc51130
This commit is contained in:
Alan Mishchenko
parent
5e0f86a2c9
commit
53c4fffa04
46
abc.plg
46
abc.plg
|
|
@ -6,30 +6,13 @@
|
|||
--------------------Configuration: abc - Win32 Release--------------------
|
||||
</h3>
|
||||
<h3>Command Lines</h3>
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA3.tmp" with contents
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3DA.tmp" with contents
|
||||
[
|
||||
/nologo /ML /W3 /GX /O2 /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /D "_MBCS" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"Release/" /Fp"Release/abc.pch" /YX /Fo"Release/" /Fd"Release/" /FD /c
|
||||
"C:\_projects\abc\src\base\abc\abcFanio.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNtk.c"
|
||||
"C:\_projects\abc\src\base\abci\abcCut.c"
|
||||
"C:\_projects\abc\src\base\seq\seqAigCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqAigIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqCreate.c"
|
||||
"C:\_projects\abc\src\base\seq\seqFpgaCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqFpgaIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqLatch.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMan.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMapCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMapIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqRetCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqRetIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqShare.c"
|
||||
"C:\_projects\abc\src\base\seq\seqUtil.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteDot.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteList.c"
|
||||
]
|
||||
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA3.tmp"
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA4.tmp" with contents
|
||||
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3DA.tmp"
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3DB.tmp" with contents
|
||||
[
|
||||
kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /incremental:no /pdb:"Release/abc.pdb" /machine:I386 /out:"_TEST/abc.exe"
|
||||
.\Release\abcAig.obj
|
||||
|
|
@ -348,29 +331,12 @@ kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32
|
|||
.\Release\mvcSort.obj
|
||||
.\Release\mvcUtils.obj
|
||||
]
|
||||
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA4.tmp"
|
||||
Creating command line "link.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3DB.tmp"
|
||||
<h3>Output Window</h3>
|
||||
Compiling...
|
||||
abcFanio.c
|
||||
abcNtk.c
|
||||
abcCut.c
|
||||
seqAigCore.c
|
||||
seqAigIter.c
|
||||
seqCreate.c
|
||||
seqFpgaCore.c
|
||||
seqFpgaIter.c
|
||||
seqLatch.c
|
||||
seqMan.c
|
||||
seqMapCore.c
|
||||
seqMapIter.c
|
||||
seqRetCore.c
|
||||
seqRetIter.c
|
||||
seqShare.c
|
||||
seqUtil.c
|
||||
ioWriteDot.c
|
||||
ioWriteList.c
|
||||
Linking...
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA6.tmp" with contents
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3DD.tmp" with contents
|
||||
[
|
||||
/nologo /o"Release/abc.bsc"
|
||||
.\Release\abcAig.sbr
|
||||
|
|
@ -688,7 +654,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA6.tmp" with cont
|
|||
.\Release\mvcPrint.sbr
|
||||
.\Release\mvcSort.sbr
|
||||
.\Release\mvcUtils.sbr]
|
||||
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP1FA6.tmp"
|
||||
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3DD.tmp"
|
||||
Creating browse info file...
|
||||
<h3>Output Window</h3>
|
||||
|
||||
|
|
|
|||
7
abc.rc
7
abc.rc
|
|
@ -53,7 +53,8 @@ alias sa set autoexec ps
|
|||
alias so source -x
|
||||
alias st strash
|
||||
alias sw sweep
|
||||
alias ssw seq_sweep
|
||||
alias ssw ssweep
|
||||
alias scl scleanup
|
||||
alias u undo
|
||||
alias wb write_blif
|
||||
alias wl write_blif
|
||||
|
|
@ -71,6 +72,6 @@ alias resynl "b; rw -l; rwz -l; b; rwz -l; b"
|
|||
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
|
||||
alias resyn2l "b; rw -l; rf -l; b; rw -l; rwz -l; b; rfz -l; rwz -l; b"
|
||||
alias thin "rwz; rfz; b; ps"
|
||||
alias choice "fsto; resynl; fsto; resyn2l; fsto; fres"
|
||||
alias t "r iscas2/s3330_edf.blif; st; seq; smap"
|
||||
alias choice "fraig_store; resynl; fraig_store; resyn2l; fraig_store; fraig_restore"
|
||||
alias t "r step_opt.blif; b; seq; show_aig; sfpga -v"
|
||||
|
||||
|
|
|
|||
|
|
@ -279,6 +279,14 @@ SOURCE=.\src\base\seq\seq.h
|
|||
# End Source File
|
||||
# Begin Source File
|
||||
|
||||
SOURCE=.\src\base\seq\seqAigCore.c
|
||||
# End Source File
|
||||
# Begin Source File
|
||||
|
||||
SOURCE=.\src\base\seq\seqAigIter.c
|
||||
# End Source File
|
||||
# Begin Source File
|
||||
|
||||
SOURCE=.\src\base\seq\seqCreate.c
|
||||
# End Source File
|
||||
# Begin Source File
|
||||
|
|
|
|||
BIN
abclib.opt
BIN
abclib.opt
Binary file not shown.
426
abclib.plg
426
abclib.plg
|
|
@ -6,13 +6,185 @@
|
|||
--------------------Configuration: abclib - Win32 Debug--------------------
|
||||
</h3>
|
||||
<h3>Command Lines</h3>
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP78F.tmp" with contents
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3E3.tmp" with contents
|
||||
[
|
||||
/nologo /MLd /W3 /Gm /GX /ZI /Od /I "src\base\abc" /I "src\base\abci" /I "src\base\abcs" /I "src\base\seq" /I "src\base\cmd" /I "src\base\io" /I "src\base\main" /I "src\bdd\cudd" /I "src\bdd\epd" /I "src\bdd\mtr" /I "src\bdd\parse" /I "src\bdd\dsd" /I "src\bdd\reo" /I "src\sop\ft" /I "src\sat\asat" /I "src\sat\msat" /I "src\sat\fraig" /I "src\opt\cut" /I "src\opt\dec" /I "src\opt\fxu" /I "src\opt\sim" /I "src\opt\rwr" /I "src\map\fpga" /I "src\map\pga" /I "src\map\mapper" /I "src\map\mapp" /I "src\map\mio" /I "src\map\super" /I "src\misc\extra" /I "src\misc\st" /I "src\misc\mvc" /I "src\misc\util" /I "src\misc\npn" /I "src\misc\vec" /D "WIN32" /D "_DEBUG" /D "_MBCS" /D "_LIB" /D "__STDC__" /D "HAVE_ASSERT_H" /FR"abclib\DebugLib/" /Fp"abclib\DebugLib/abclib.pch" /YX /Fo"abclib\DebugLib/" /Fd"abclib\DebugLib/" /FD /GZ /c
|
||||
"C:\_projects\abc\src\base\abc\abcAig.c"
|
||||
"C:\_projects\abc\src\base\abc\abcCheck.c"
|
||||
"C:\_projects\abc\src\base\abc\abcDfs.c"
|
||||
"C:\_projects\abc\src\base\abc\abcFanio.c"
|
||||
"C:\_projects\abc\src\base\abc\abcFunc.c"
|
||||
"C:\_projects\abc\src\base\abc\abcLatch.c"
|
||||
"C:\_projects\abc\src\base\abc\abcMinBase.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNames.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNetlist.c"
|
||||
"C:\_projects\abc\src\base\abc\abcNtk.c"
|
||||
"C:\_projects\abc\src\base\abc\abcObj.c"
|
||||
"C:\_projects\abc\src\base\abc\abcRefs.c"
|
||||
"C:\_projects\abc\src\base\abc\abcShow.c"
|
||||
"C:\_projects\abc\src\base\abc\abcSop.c"
|
||||
"C:\_projects\abc\src\base\abc\abcUtil.c"
|
||||
"C:\_projects\abc\src\base\abci\abc.c"
|
||||
"C:\_projects\abc\src\base\abci\abcAttach.c"
|
||||
"C:\_projects\abc\src\base\abci\abcBalance.c"
|
||||
"C:\_projects\abc\src\base\abci\abcCollapse.c"
|
||||
"C:\_projects\abc\src\base\abci\abcCut.c"
|
||||
"C:\_projects\abc\src\base\abci\abcDsd.c"
|
||||
"C:\_projects\abc\src\base\abci\abcFpga.c"
|
||||
"C:\_projects\abc\src\base\abci\abcFraig.c"
|
||||
"C:\_projects\abc\src\base\abci\abcFxu.c"
|
||||
"C:\_projects\abc\src\base\abci\abcMap.c"
|
||||
"C:\_projects\abc\src\base\abci\abcMiter.c"
|
||||
"C:\_projects\abc\src\base\abci\abcNtbdd.c"
|
||||
"C:\_projects\abc\src\base\abci\abcPga.c"
|
||||
"C:\_projects\abc\src\base\abci\abcPrint.c"
|
||||
"C:\_projects\abc\src\base\abci\abcReconv.c"
|
||||
"C:\_projects\abc\src\base\abci\abcRefactor.c"
|
||||
"C:\_projects\abc\src\base\abci\abcRenode.c"
|
||||
"C:\_projects\abc\src\base\abci\abcRewrite.c"
|
||||
"C:\_projects\abc\src\base\abci\abcSat.c"
|
||||
"C:\_projects\abc\src\base\abci\abcStrash.c"
|
||||
"C:\_projects\abc\src\base\abci\abcSweep.c"
|
||||
"C:\_projects\abc\src\base\abci\abcSymm.c"
|
||||
"C:\_projects\abc\src\base\abci\abcTiming.c"
|
||||
"C:\_projects\abc\src\base\abci\abcUnreach.c"
|
||||
"C:\_projects\abc\src\base\abci\abcVanEijk.c"
|
||||
"C:\_projects\abc\src\base\abci\abcVanImp.c"
|
||||
"C:\_projects\abc\src\base\abci\abcVerify.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmd.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdAlias.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdApi.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdFlag.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdHist.c"
|
||||
"C:\_projects\abc\src\base\cmd\cmdUtils.c"
|
||||
"C:\_projects\abc\src\base\io\io.c"
|
||||
"C:\_projects\abc\src\base\io\ioRead.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadBaf.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadBench.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadBlif.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadEdif.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadEqn.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadPla.c"
|
||||
"C:\_projects\abc\src\base\io\ioReadVerilog.c"
|
||||
"C:\_projects\abc\src\base\io\ioUtil.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteBaf.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteBench.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteBlif.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteCnf.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteDot.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteEqn.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteGml.c"
|
||||
"C:\_projects\abc\src\base\io\ioWriteList.c"
|
||||
"C:\_projects\abc\src\base\io\ioWritePla.c"
|
||||
"C:\_projects\abc\src\base\main\libSupport.c"
|
||||
"C:\_projects\abc\src\base\main\main.c"
|
||||
"C:\_projects\abc\src\base\main\mainFrame.c"
|
||||
"C:\_projects\abc\src\base\main\mainInit.c"
|
||||
"C:\_projects\abc\src\base\main\mainUtils.c"
|
||||
"C:\_projects\abc\src\sat\csat\csat_apis.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxu.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuCreate.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuHeapD.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuHeapS.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuList.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuMatrix.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuPair.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuPrint.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuReduce.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuSelect.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuSingle.c"
|
||||
"C:\_projects\abc\src\opt\fxu\fxuUpdate.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrDec.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrEva.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrExp.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrLib.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrMan.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrPrint.c"
|
||||
"C:\_projects\abc\src\opt\rwr\rwrUtil.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutApi.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutCut.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutMan.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutMerge.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutNode.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutOracle.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutSeq.c"
|
||||
"C:\_projects\abc\src\opt\cut\cutTruth.c"
|
||||
"C:\_projects\abc\src\opt\dec\decAbc.c"
|
||||
"C:\_projects\abc\src\opt\dec\decFactor.c"
|
||||
"C:\_projects\abc\src\opt\dec\decMan.c"
|
||||
"C:\_projects\abc\src\opt\dec\decPrint.c"
|
||||
"C:\_projects\abc\src\opt\dec\decUtil.c"
|
||||
"C:\_projects\abc\src\opt\sim\simMan.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSat.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSeq.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSupp.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSwitch.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSym.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSymSat.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSymSim.c"
|
||||
"C:\_projects\abc\src\opt\sim\simSymStr.c"
|
||||
"C:\_projects\abc\src\opt\sim\simUtils.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpga.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCore.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCreate.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCut.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaCutUtils.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaFanout.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaLib.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaMatch.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaSwitch.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaTime.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaTruth.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaUtils.c"
|
||||
"C:\_projects\abc\src\map\fpga\fpgaVec.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapper.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCanon.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCore.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCreate.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCut.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperCutUtils.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperFanout.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperLib.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperMatch.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperRefs.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperSuper.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperSwitch.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTable.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTime.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTree.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperTruth.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperUtils.c"
|
||||
"C:\_projects\abc\src\map\mapper\mapperVec.c"
|
||||
"C:\_projects\abc\src\map\mio\mio.c"
|
||||
"C:\_projects\abc\src\map\mio\mioApi.c"
|
||||
"C:\_projects\abc\src\map\mio\mioFunc.c"
|
||||
"C:\_projects\abc\src\map\mio\mioRead.c"
|
||||
"C:\_projects\abc\src\map\mio\mioUtils.c"
|
||||
"C:\_projects\abc\src\map\super\super.c"
|
||||
"C:\_projects\abc\src\map\super\superAnd.c"
|
||||
"C:\_projects\abc\src\map\super\superGate.c"
|
||||
"C:\_projects\abc\src\map\super\superWrite.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaCore.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaMan.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaMatch.c"
|
||||
"C:\_projects\abc\src\map\pga\pgaUtil.c"
|
||||
"C:\_projects\abc\src\misc\extra\extraUtilReader.c"
|
||||
"C:\_projects\abc\src\base\seq\seqUtil.c"
|
||||
"C:\_projects\abc\src\base\seq\seqAigCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqAigIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqCreate.c"
|
||||
"C:\_projects\abc\src\base\seq\seqFpgaCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqFpgaIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqLatch.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMan.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMapCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqMapIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqRetCore.c"
|
||||
"C:\_projects\abc\src\base\seq\seqRetIter.c"
|
||||
"C:\_projects\abc\src\base\seq\seqShare.c"
|
||||
]
|
||||
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP78F.tmp"
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with contents
|
||||
Creating command line "cl.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3E3.tmp"
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3E4.tmp" with contents
|
||||
[
|
||||
/nologo /out:"abclib\abclib_debug.lib"
|
||||
.\abclib\DebugLib\abcAig.obj
|
||||
|
|
@ -42,6 +214,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\abcMap.obj
|
||||
.\abclib\DebugLib\abcMiter.obj
|
||||
.\abclib\DebugLib\abcNtbdd.obj
|
||||
.\abclib\DebugLib\abcPga.obj
|
||||
.\abclib\DebugLib\abcPrint.obj
|
||||
.\abclib\DebugLib\abcReconv.obj
|
||||
.\abclib\DebugLib\abcRefactor.obj
|
||||
|
|
@ -53,6 +226,8 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\abcSymm.obj
|
||||
.\abclib\DebugLib\abcTiming.obj
|
||||
.\abclib\DebugLib\abcUnreach.obj
|
||||
.\abclib\DebugLib\abcVanEijk.obj
|
||||
.\abclib\DebugLib\abcVanImp.obj
|
||||
.\abclib\DebugLib\abcVerify.obj
|
||||
.\abclib\DebugLib\cmd.obj
|
||||
.\abclib\DebugLib\cmdAlias.obj
|
||||
|
|
@ -62,6 +237,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\cmdUtils.obj
|
||||
.\abclib\DebugLib\io.obj
|
||||
.\abclib\DebugLib\ioRead.obj
|
||||
.\abclib\DebugLib\ioReadBaf.obj
|
||||
.\abclib\DebugLib\ioReadBench.obj
|
||||
.\abclib\DebugLib\ioReadBlif.obj
|
||||
.\abclib\DebugLib\ioReadEdif.obj
|
||||
|
|
@ -69,13 +245,16 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\ioReadPla.obj
|
||||
.\abclib\DebugLib\ioReadVerilog.obj
|
||||
.\abclib\DebugLib\ioUtil.obj
|
||||
.\abclib\DebugLib\ioWriteBaf.obj
|
||||
.\abclib\DebugLib\ioWriteBench.obj
|
||||
.\abclib\DebugLib\ioWriteBlif.obj
|
||||
.\abclib\DebugLib\ioWriteCnf.obj
|
||||
.\abclib\DebugLib\ioWriteDot.obj
|
||||
.\abclib\DebugLib\ioWriteEqn.obj
|
||||
.\abclib\DebugLib\ioWriteGml.obj
|
||||
.\abclib\DebugLib\ioWriteList.obj
|
||||
.\abclib\DebugLib\ioWritePla.obj
|
||||
.\abclib\DebugLib\libSupport.obj
|
||||
.\abclib\DebugLib\main.obj
|
||||
.\abclib\DebugLib\mainFrame.obj
|
||||
.\abclib\DebugLib\mainInit.obj
|
||||
|
|
@ -207,9 +386,12 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\rwrMan.obj
|
||||
.\abclib\DebugLib\rwrPrint.obj
|
||||
.\abclib\DebugLib\rwrUtil.obj
|
||||
.\abclib\DebugLib\cutApi.obj
|
||||
.\abclib\DebugLib\cutCut.obj
|
||||
.\abclib\DebugLib\cutMan.obj
|
||||
.\abclib\DebugLib\cutMerge.obj
|
||||
.\abclib\DebugLib\cutNode.obj
|
||||
.\abclib\DebugLib\cutOracle.obj
|
||||
.\abclib\DebugLib\cutSeq.obj
|
||||
.\abclib\DebugLib\cutTruth.obj
|
||||
.\abclib\DebugLib\decAbc.obj
|
||||
|
|
@ -219,6 +401,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\decUtil.obj
|
||||
.\abclib\DebugLib\simMan.obj
|
||||
.\abclib\DebugLib\simSat.obj
|
||||
.\abclib\DebugLib\simSeq.obj
|
||||
.\abclib\DebugLib\simSupp.obj
|
||||
.\abclib\DebugLib\simSwitch.obj
|
||||
.\abclib\DebugLib\simSym.obj
|
||||
|
|
@ -266,6 +449,11 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\superAnd.obj
|
||||
.\abclib\DebugLib\superGate.obj
|
||||
.\abclib\DebugLib\superWrite.obj
|
||||
.\abclib\DebugLib\pgaCore.obj
|
||||
.\abclib\DebugLib\pgaMan.obj
|
||||
.\abclib\DebugLib\pgaMatch.obj
|
||||
.\abclib\DebugLib\pgaUtil.obj
|
||||
.\abclib\DebugLib\extraBddKmap.obj
|
||||
.\abclib\DebugLib\extraBddMisc.obj
|
||||
.\abclib\DebugLib\extraBddSymm.obj
|
||||
.\abclib\DebugLib\extraUtilBitMatrix.obj
|
||||
|
|
@ -301,10 +489,9 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\mvcPrint.obj
|
||||
.\abclib\DebugLib\mvcSort.obj
|
||||
.\abclib\DebugLib\mvcUtils.obj
|
||||
.\abclib\DebugLib\abcVanImp.obj
|
||||
.\abclib\DebugLib\abcPga.obj
|
||||
.\abclib\DebugLib\abcVanEijk.obj
|
||||
.\abclib\DebugLib\seqUtil.obj
|
||||
.\abclib\DebugLib\seqAigCore.obj
|
||||
.\abclib\DebugLib\seqAigIter.obj
|
||||
.\abclib\DebugLib\seqCreate.obj
|
||||
.\abclib\DebugLib\seqFpgaCore.obj
|
||||
.\abclib\DebugLib\seqFpgaIter.obj
|
||||
|
|
@ -315,26 +502,185 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp" with conte
|
|||
.\abclib\DebugLib\seqRetCore.obj
|
||||
.\abclib\DebugLib\seqRetIter.obj
|
||||
.\abclib\DebugLib\seqShare.obj
|
||||
.\abclib\DebugLib\ioWriteList.obj
|
||||
.\abclib\DebugLib\ioReadBaf.obj
|
||||
.\abclib\DebugLib\ioWriteBaf.obj
|
||||
.\abclib\DebugLib\simSeq.obj
|
||||
.\abclib\DebugLib\extraBddKmap.obj
|
||||
.\abclib\DebugLib\cutOracle.obj
|
||||
.\abclib\DebugLib\cutApi.obj
|
||||
.\abclib\DebugLib\cutCut.obj
|
||||
.\abclib\DebugLib\libSupport.obj
|
||||
.\abclib\DebugLib\pgaUtil.obj
|
||||
.\abclib\DebugLib\pgaCore.obj
|
||||
.\abclib\DebugLib\pgaMan.obj
|
||||
.\abclib\DebugLib\pgaMatch.obj
|
||||
]
|
||||
Creating command line "link.exe -lib @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP790.tmp"
|
||||
Creating command line "link.exe -lib @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3E4.tmp"
|
||||
<h3>Output Window</h3>
|
||||
Compiling...
|
||||
abcAig.c
|
||||
abcCheck.c
|
||||
abcDfs.c
|
||||
abcFanio.c
|
||||
abcFunc.c
|
||||
abcLatch.c
|
||||
abcMinBase.c
|
||||
abcNames.c
|
||||
abcNetlist.c
|
||||
abcNtk.c
|
||||
abcObj.c
|
||||
abcRefs.c
|
||||
abcShow.c
|
||||
abcSop.c
|
||||
abcUtil.c
|
||||
abc.c
|
||||
abcAttach.c
|
||||
abcBalance.c
|
||||
abcCollapse.c
|
||||
abcCut.c
|
||||
abcDsd.c
|
||||
abcFpga.c
|
||||
abcFraig.c
|
||||
abcFxu.c
|
||||
abcMap.c
|
||||
abcMiter.c
|
||||
abcNtbdd.c
|
||||
abcPga.c
|
||||
abcPrint.c
|
||||
abcReconv.c
|
||||
abcRefactor.c
|
||||
abcRenode.c
|
||||
abcRewrite.c
|
||||
abcSat.c
|
||||
abcStrash.c
|
||||
abcSweep.c
|
||||
abcSymm.c
|
||||
abcTiming.c
|
||||
abcUnreach.c
|
||||
abcVanEijk.c
|
||||
abcVanImp.c
|
||||
abcVerify.c
|
||||
cmd.c
|
||||
cmdAlias.c
|
||||
cmdApi.c
|
||||
cmdFlag.c
|
||||
cmdHist.c
|
||||
cmdUtils.c
|
||||
io.c
|
||||
ioRead.c
|
||||
ioReadBaf.c
|
||||
ioReadBench.c
|
||||
ioReadBlif.c
|
||||
ioReadEdif.c
|
||||
ioReadEqn.c
|
||||
ioReadPla.c
|
||||
ioReadVerilog.c
|
||||
ioUtil.c
|
||||
ioWriteBaf.c
|
||||
ioWriteBench.c
|
||||
ioWriteBlif.c
|
||||
ioWriteCnf.c
|
||||
ioWriteDot.c
|
||||
ioWriteEqn.c
|
||||
ioWriteGml.c
|
||||
ioWriteList.c
|
||||
ioWritePla.c
|
||||
libSupport.c
|
||||
main.c
|
||||
mainFrame.c
|
||||
mainInit.c
|
||||
mainUtils.c
|
||||
csat_apis.c
|
||||
fxu.c
|
||||
fxuCreate.c
|
||||
fxuHeapD.c
|
||||
fxuHeapS.c
|
||||
fxuList.c
|
||||
fxuMatrix.c
|
||||
fxuPair.c
|
||||
fxuPrint.c
|
||||
fxuReduce.c
|
||||
fxuSelect.c
|
||||
fxuSingle.c
|
||||
fxuUpdate.c
|
||||
rwrDec.c
|
||||
rwrEva.c
|
||||
rwrExp.c
|
||||
rwrLib.c
|
||||
rwrMan.c
|
||||
rwrPrint.c
|
||||
rwrUtil.c
|
||||
cutApi.c
|
||||
cutCut.c
|
||||
cutMan.c
|
||||
cutMerge.c
|
||||
cutNode.c
|
||||
cutOracle.c
|
||||
cutSeq.c
|
||||
cutTruth.c
|
||||
decAbc.c
|
||||
decFactor.c
|
||||
decMan.c
|
||||
decPrint.c
|
||||
decUtil.c
|
||||
simMan.c
|
||||
simSat.c
|
||||
simSeq.c
|
||||
simSupp.c
|
||||
simSwitch.c
|
||||
simSym.c
|
||||
simSymSat.c
|
||||
simSymSim.c
|
||||
simSymStr.c
|
||||
simUtils.c
|
||||
fpga.c
|
||||
fpgaCore.c
|
||||
fpgaCreate.c
|
||||
fpgaCut.c
|
||||
fpgaCutUtils.c
|
||||
fpgaFanout.c
|
||||
fpgaLib.c
|
||||
fpgaMatch.c
|
||||
fpgaSwitch.c
|
||||
fpgaTime.c
|
||||
fpgaTruth.c
|
||||
fpgaUtils.c
|
||||
fpgaVec.c
|
||||
mapper.c
|
||||
mapperCanon.c
|
||||
mapperCore.c
|
||||
mapperCreate.c
|
||||
mapperCut.c
|
||||
mapperCutUtils.c
|
||||
mapperFanout.c
|
||||
mapperLib.c
|
||||
mapperMatch.c
|
||||
mapperRefs.c
|
||||
mapperSuper.c
|
||||
mapperSwitch.c
|
||||
mapperTable.c
|
||||
mapperTime.c
|
||||
mapperTree.c
|
||||
mapperTruth.c
|
||||
mapperUtils.c
|
||||
mapperVec.c
|
||||
mio.c
|
||||
mioApi.c
|
||||
mioFunc.c
|
||||
mioRead.c
|
||||
mioUtils.c
|
||||
super.c
|
||||
superAnd.c
|
||||
superGate.c
|
||||
superWrite.c
|
||||
pgaCore.c
|
||||
pgaMan.c
|
||||
pgaMatch.c
|
||||
pgaUtil.c
|
||||
extraUtilReader.c
|
||||
seqUtil.c
|
||||
seqAigCore.c
|
||||
seqAigIter.c
|
||||
seqCreate.c
|
||||
seqFpgaCore.c
|
||||
seqFpgaIter.c
|
||||
seqLatch.c
|
||||
seqMan.c
|
||||
seqMapCore.c
|
||||
seqMapIter.c
|
||||
seqRetCore.c
|
||||
seqRetIter.c
|
||||
seqShare.c
|
||||
Creating library...
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with contents
|
||||
Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3E5.tmp" with contents
|
||||
[
|
||||
/nologo /o"abclib\DebugLib/abclib.bsc"
|
||||
.\abclib\DebugLib\abcAig.sbr
|
||||
|
|
@ -364,6 +710,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\abcMap.sbr
|
||||
.\abclib\DebugLib\abcMiter.sbr
|
||||
.\abclib\DebugLib\abcNtbdd.sbr
|
||||
.\abclib\DebugLib\abcPga.sbr
|
||||
.\abclib\DebugLib\abcPrint.sbr
|
||||
.\abclib\DebugLib\abcReconv.sbr
|
||||
.\abclib\DebugLib\abcRefactor.sbr
|
||||
|
|
@ -375,6 +722,8 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\abcSymm.sbr
|
||||
.\abclib\DebugLib\abcTiming.sbr
|
||||
.\abclib\DebugLib\abcUnreach.sbr
|
||||
.\abclib\DebugLib\abcVanEijk.sbr
|
||||
.\abclib\DebugLib\abcVanImp.sbr
|
||||
.\abclib\DebugLib\abcVerify.sbr
|
||||
.\abclib\DebugLib\cmd.sbr
|
||||
.\abclib\DebugLib\cmdAlias.sbr
|
||||
|
|
@ -384,6 +733,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\cmdUtils.sbr
|
||||
.\abclib\DebugLib\io.sbr
|
||||
.\abclib\DebugLib\ioRead.sbr
|
||||
.\abclib\DebugLib\ioReadBaf.sbr
|
||||
.\abclib\DebugLib\ioReadBench.sbr
|
||||
.\abclib\DebugLib\ioReadBlif.sbr
|
||||
.\abclib\DebugLib\ioReadEdif.sbr
|
||||
|
|
@ -391,13 +741,16 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\ioReadPla.sbr
|
||||
.\abclib\DebugLib\ioReadVerilog.sbr
|
||||
.\abclib\DebugLib\ioUtil.sbr
|
||||
.\abclib\DebugLib\ioWriteBaf.sbr
|
||||
.\abclib\DebugLib\ioWriteBench.sbr
|
||||
.\abclib\DebugLib\ioWriteBlif.sbr
|
||||
.\abclib\DebugLib\ioWriteCnf.sbr
|
||||
.\abclib\DebugLib\ioWriteDot.sbr
|
||||
.\abclib\DebugLib\ioWriteEqn.sbr
|
||||
.\abclib\DebugLib\ioWriteGml.sbr
|
||||
.\abclib\DebugLib\ioWriteList.sbr
|
||||
.\abclib\DebugLib\ioWritePla.sbr
|
||||
.\abclib\DebugLib\libSupport.sbr
|
||||
.\abclib\DebugLib\main.sbr
|
||||
.\abclib\DebugLib\mainFrame.sbr
|
||||
.\abclib\DebugLib\mainInit.sbr
|
||||
|
|
@ -529,9 +882,12 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\rwrMan.sbr
|
||||
.\abclib\DebugLib\rwrPrint.sbr
|
||||
.\abclib\DebugLib\rwrUtil.sbr
|
||||
.\abclib\DebugLib\cutApi.sbr
|
||||
.\abclib\DebugLib\cutCut.sbr
|
||||
.\abclib\DebugLib\cutMan.sbr
|
||||
.\abclib\DebugLib\cutMerge.sbr
|
||||
.\abclib\DebugLib\cutNode.sbr
|
||||
.\abclib\DebugLib\cutOracle.sbr
|
||||
.\abclib\DebugLib\cutSeq.sbr
|
||||
.\abclib\DebugLib\cutTruth.sbr
|
||||
.\abclib\DebugLib\decAbc.sbr
|
||||
|
|
@ -541,6 +897,7 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\decUtil.sbr
|
||||
.\abclib\DebugLib\simMan.sbr
|
||||
.\abclib\DebugLib\simSat.sbr
|
||||
.\abclib\DebugLib\simSeq.sbr
|
||||
.\abclib\DebugLib\simSupp.sbr
|
||||
.\abclib\DebugLib\simSwitch.sbr
|
||||
.\abclib\DebugLib\simSym.sbr
|
||||
|
|
@ -588,6 +945,11 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\superAnd.sbr
|
||||
.\abclib\DebugLib\superGate.sbr
|
||||
.\abclib\DebugLib\superWrite.sbr
|
||||
.\abclib\DebugLib\pgaCore.sbr
|
||||
.\abclib\DebugLib\pgaMan.sbr
|
||||
.\abclib\DebugLib\pgaMatch.sbr
|
||||
.\abclib\DebugLib\pgaUtil.sbr
|
||||
.\abclib\DebugLib\extraBddKmap.sbr
|
||||
.\abclib\DebugLib\extraBddMisc.sbr
|
||||
.\abclib\DebugLib\extraBddSymm.sbr
|
||||
.\abclib\DebugLib\extraUtilBitMatrix.sbr
|
||||
|
|
@ -623,10 +985,9 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\mvcPrint.sbr
|
||||
.\abclib\DebugLib\mvcSort.sbr
|
||||
.\abclib\DebugLib\mvcUtils.sbr
|
||||
.\abclib\DebugLib\abcVanImp.sbr
|
||||
.\abclib\DebugLib\abcPga.sbr
|
||||
.\abclib\DebugLib\abcVanEijk.sbr
|
||||
.\abclib\DebugLib\seqUtil.sbr
|
||||
.\abclib\DebugLib\seqAigCore.sbr
|
||||
.\abclib\DebugLib\seqAigIter.sbr
|
||||
.\abclib\DebugLib\seqCreate.sbr
|
||||
.\abclib\DebugLib\seqFpgaCore.sbr
|
||||
.\abclib\DebugLib\seqFpgaIter.sbr
|
||||
|
|
@ -636,21 +997,8 @@ Creating temporary file "C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp" with conte
|
|||
.\abclib\DebugLib\seqMapIter.sbr
|
||||
.\abclib\DebugLib\seqRetCore.sbr
|
||||
.\abclib\DebugLib\seqRetIter.sbr
|
||||
.\abclib\DebugLib\seqShare.sbr
|
||||
.\abclib\DebugLib\ioWriteList.sbr
|
||||
.\abclib\DebugLib\ioReadBaf.sbr
|
||||
.\abclib\DebugLib\ioWriteBaf.sbr
|
||||
.\abclib\DebugLib\simSeq.sbr
|
||||
.\abclib\DebugLib\extraBddKmap.sbr
|
||||
.\abclib\DebugLib\cutOracle.sbr
|
||||
.\abclib\DebugLib\cutApi.sbr
|
||||
.\abclib\DebugLib\cutCut.sbr
|
||||
.\abclib\DebugLib\libSupport.sbr
|
||||
.\abclib\DebugLib\pgaUtil.sbr
|
||||
.\abclib\DebugLib\pgaCore.sbr
|
||||
.\abclib\DebugLib\pgaMan.sbr
|
||||
.\abclib\DebugLib\pgaMatch.sbr]
|
||||
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP791.tmp"
|
||||
.\abclib\DebugLib\seqShare.sbr]
|
||||
Creating command line "bscmake.exe @C:\DOCUME~1\alanmi\LOCALS~1\Temp\RSP3E5.tmp"
|
||||
Creating browse info file...
|
||||
<h3>Output Window</h3>
|
||||
|
||||
|
|
|
|||
|
|
@ -632,8 +632,9 @@ extern Abc_Ntk_t * Abc_NtkStrash( Abc_Ntk_t * pNtk, bool fAllNodes, bool
|
|||
extern Abc_Obj_t * Abc_NodeStrash( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode );
|
||||
extern int Abc_NtkAppend( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2 );
|
||||
/*=== abcSweep.c ==========================================================*/
|
||||
extern int Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Abc_NtkSweep( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Abc_NtkReduceNodes( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes );
|
||||
/*=== abcTiming.c ==========================================================*/
|
||||
extern Abc_Time_t * Abc_NodeReadArrival( Abc_Obj_t * pNode );
|
||||
extern Abc_Time_t * Abc_NodeReadRequired( Abc_Obj_t * pNode );
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
/// DECLARATIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
static void Abc_NtkAddPoBuffers( Abc_Ntk_t * pNtk );
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// FUNCTION DEFINITIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -280,7 +282,17 @@ Abc_Ntk_t * Abc_NtkAigToLogicSop( Abc_Ntk_t * pNtk )
|
|||
else
|
||||
Abc_ObjAddFanin( pObj->pCopy, pFanin->pCopy );
|
||||
// connect the COs
|
||||
Abc_NtkFinalize( pNtk, pNtkNew );
|
||||
// Abc_NtkFinalize( pNtk, pNtkNew );
|
||||
Abc_NtkForEachCo( pNtk, pObj, i )
|
||||
{
|
||||
pFanin = Abc_ObjFanin0(pObj);
|
||||
if ( pFanin->pCopy->pCopy )
|
||||
pNodeNew = Abc_ObjNotCond(pFanin->pCopy->pCopy, Abc_ObjFaninC0(pObj));
|
||||
else
|
||||
pNodeNew = Abc_ObjNotCond(pFanin->pCopy, Abc_ObjFaninC0(pObj));
|
||||
Abc_ObjAddFanin( pObj->pCopy, pNodeNew );
|
||||
}
|
||||
|
||||
// fix the problem with complemented and duplicated CO edges
|
||||
Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 );
|
||||
// duplicate the EXDC Ntk
|
||||
|
|
@ -364,6 +376,31 @@ Abc_Ntk_t * Abc_NtkAigToLogicSopBench( Abc_Ntk_t * pNtk )
|
|||
return pNtkNew;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Adds buffers for each PO.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Abc_NtkAddPoBuffers( Abc_Ntk_t * pNtk )
|
||||
{
|
||||
Abc_Obj_t * pObj, * pFanin, * pFaninNew;
|
||||
int i;
|
||||
assert( Abc_NtkIsStrash(pNtk) );
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
{
|
||||
pFanin = Abc_ObjChild0(pObj);
|
||||
pFaninNew = Abc_NtkCreateNode(pNtk);
|
||||
Abc_ObjAddFanin( pFaninNew, pFanin );
|
||||
Abc_ObjPatchFanin( pObj, pFanin, pFaninNew );
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -102,6 +102,7 @@ static int Abc_CommandRetime ( Abc_Frame_t * pAbc, int argc, char ** argv
|
|||
static int Abc_CommandSeqFpga ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandSeqMap ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandSeqSweep ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandSeqCleanup ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
|
||||
static int Abc_CommandCec ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
static int Abc_CommandSec ( Abc_Frame_t * pAbc, int argc, char ** argv );
|
||||
|
|
@ -195,7 +196,8 @@ void Abc_Init( Abc_Frame_t * pAbc )
|
|||
Cmd_CommandAdd( pAbc, "Sequential", "retime", Abc_CommandRetime, 1 );
|
||||
Cmd_CommandAdd( pAbc, "Sequential", "sfpga", Abc_CommandSeqFpga, 1 );
|
||||
Cmd_CommandAdd( pAbc, "Sequential", "smap", Abc_CommandSeqMap, 1 );
|
||||
Cmd_CommandAdd( pAbc, "Sequential", "seq_sweep", Abc_CommandSeqSweep, 1 );
|
||||
Cmd_CommandAdd( pAbc, "Sequential", "ssweep", Abc_CommandSeqSweep, 1 );
|
||||
Cmd_CommandAdd( pAbc, "Sequential", "scleanup", Abc_CommandSeqCleanup, 1 );
|
||||
|
||||
Cmd_CommandAdd( pAbc, "Verification", "cec", Abc_CommandCec, 0 );
|
||||
Cmd_CommandAdd( pAbc, "Verification", "sec", Abc_CommandSec, 0 );
|
||||
|
|
@ -1299,7 +1301,7 @@ int Abc_CommandShowNtk( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
{
|
||||
switch ( c )
|
||||
{
|
||||
case 'n':
|
||||
case 'g':
|
||||
fGateNames ^= 1;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -1716,7 +1718,7 @@ int Abc_CommandCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
return 1;
|
||||
}
|
||||
// modify the current network
|
||||
Abc_NtkCleanup( pNtk, 0 );
|
||||
Abc_NtkCleanup( pNtk, 1 );
|
||||
return 0;
|
||||
|
||||
usage:
|
||||
|
|
@ -5132,7 +5134,7 @@ int Abc_CommandRetime( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
if ( pNtkRes == NULL )
|
||||
{
|
||||
fprintf( pErr, "Retiming has failed.\n" );
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
// replace the current network
|
||||
Abc_FrameReplaceCurrentNetwork( pAbc, pNtkRes );
|
||||
|
|
@ -5208,12 +5210,14 @@ int Abc_CommandSeqFpga( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
|
||||
if ( Abc_NtkHasAig(pNtk) )
|
||||
{
|
||||
/*
|
||||
// quit if there are choice nodes
|
||||
if ( Abc_NtkGetChoiceNum(pNtk) )
|
||||
{
|
||||
fprintf( pErr, "Currently cannot map/retime networks with choice nodes.\n" );
|
||||
return 0;
|
||||
}
|
||||
*/
|
||||
if ( Abc_NtkIsStrash(pNtk) )
|
||||
pNtkNew = Abc_NtkAigToSeq(pNtk);
|
||||
else
|
||||
|
|
@ -5330,12 +5334,14 @@ int Abc_CommandSeqMap( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
|
||||
if ( Abc_NtkHasAig(pNtk) )
|
||||
{
|
||||
/*
|
||||
// quit if there are choice nodes
|
||||
if ( Abc_NtkGetChoiceNum(pNtk) )
|
||||
{
|
||||
fprintf( pErr, "Currently cannot map/retime networks with choice nodes.\n" );
|
||||
return 0;
|
||||
}
|
||||
*/
|
||||
if ( Abc_NtkIsStrash(pNtk) )
|
||||
pNtkNew = Abc_NtkAigToSeq(pNtk);
|
||||
else
|
||||
|
|
@ -5377,7 +5383,7 @@ int Abc_CommandSeqMap( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
{
|
||||
fprintf( pErr, "Sequential FPGA mapping has failed.\n" );
|
||||
Abc_NtkDelete( pNtkNew );
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
Abc_NtkDelete( pNtkNew );
|
||||
|
||||
|
|
@ -5497,7 +5503,7 @@ int Abc_CommandSeqSweep( Abc_Frame_t * pAbc, int argc, char ** argv )
|
|||
return 0;
|
||||
|
||||
usage:
|
||||
fprintf( pErr, "usage: seq_sweep [-F num] [-eivh]\n" );
|
||||
fprintf( pErr, "usage: ssweep [-F num] [-eivh]\n" );
|
||||
fprintf( pErr, "\t performs sequential sweep using van Eijk's method\n" );
|
||||
fprintf( pErr, "\t-F num : number of time frames in the base case [default = %d]\n", nFrames );
|
||||
fprintf( pErr, "\t-e : toggle writing EXDC network [default = %s]\n", fExdc? "yes": "no" );
|
||||
|
|
@ -5507,6 +5513,60 @@ usage:
|
|||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis []
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Abc_CommandSeqCleanup( Abc_Frame_t * pAbc, int argc, char ** argv )
|
||||
{
|
||||
FILE * pOut, * pErr;
|
||||
Abc_Ntk_t * pNtk;
|
||||
int c;
|
||||
|
||||
pNtk = Abc_FrameReadNet(pAbc);
|
||||
pOut = Abc_FrameReadOut(pAbc);
|
||||
pErr = Abc_FrameReadErr(pAbc);
|
||||
|
||||
// set defaults
|
||||
util_getopt_reset();
|
||||
while ( ( c = util_getopt( argc, argv, "h" ) ) != EOF )
|
||||
{
|
||||
switch ( c )
|
||||
{
|
||||
case 'h':
|
||||
goto usage;
|
||||
default:
|
||||
goto usage;
|
||||
}
|
||||
}
|
||||
if ( pNtk == NULL )
|
||||
{
|
||||
fprintf( pErr, "Empty network.\n" );
|
||||
return 1;
|
||||
}
|
||||
if ( !Abc_NtkIsSeq(pNtk) )
|
||||
{
|
||||
fprintf( pErr, "Only works for sequential AIGs.\n" );
|
||||
return 1;
|
||||
}
|
||||
// modify the current network
|
||||
Seq_NtkCleanup( pNtk, 1 );
|
||||
return 0;
|
||||
|
||||
usage:
|
||||
fprintf( pErr, "usage: scleanup [-h]\n" );
|
||||
fprintf( pErr, "\t performs sequential cleanup\n" );
|
||||
fprintf( pErr, "\t-h : print the command usage\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
|
|
|||
|
|
@ -96,6 +96,57 @@ void Abc_NtkPrintStats( FILE * pFile, Abc_Ntk_t * pNtk, int fFactored )
|
|||
fprintf( pFile, " lev = %3d", Abc_NtkGetLevelNum(pNtk) );
|
||||
|
||||
fprintf( pFile, "\n" );
|
||||
// print the statistic into a file
|
||||
/*
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%4d ", Abc_NtkPiNum(pNtk) );
|
||||
fprintf( pTable, "%4d ", Abc_NtkPoNum(pNtk) );
|
||||
// fprintf( pTable, "%4d ", Abc_NtkLatchNum(pNtk) );
|
||||
fprintf( pTable, "%6d ", Abc_NtkNodeNum(pNtk) );
|
||||
fprintf( pTable, "%6d ", Abc_AigGetLevelNum(pNtk) );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
/*
|
||||
// print the statistic into a file
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pSpec );
|
||||
fprintf( pTable, "%.0f ", Abc_NtkGetMappedArea(pNtk) );
|
||||
fprintf( pTable, "%.2f ", Abc_NtkDelayTrace(pNtk) );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
// print the statistic into a file
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%d ", Abc_NtkNodeNum(pNtk) );
|
||||
fprintf( pTable, "%d ", Abc_AigGetLevelNum(pNtk) );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
/*
|
||||
// print the statistic into a file
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%d ", Abc_NtkLatchNum(pNtk) );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
|
|
|||
|
|
@ -447,17 +447,40 @@ int Abc_NodeDroppingCost( Abc_Obj_t * pNode )
|
|||
int Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Vec_Ptr_t * vNodes;
|
||||
Abc_Obj_t * pNode;
|
||||
int i, Counter;
|
||||
int Counter;
|
||||
assert( !Abc_NtkHasAig(pNtk) );
|
||||
// mark the nodes reachable from the POs
|
||||
vNodes = Abc_NtkDfs( pNtk, 0 );
|
||||
Counter = Abc_NtkReduceNodes( pNtk, vNodes );
|
||||
if ( fVerbose )
|
||||
printf( "Cleanup removed %d dangling nodes.\n", Counter );
|
||||
Vec_PtrFree( vNodes );
|
||||
return Counter;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Preserves the nodes collected in the array.]
|
||||
|
||||
Description [Returns the number of nodes removed.]
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Abc_NtkReduceNodes( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes )
|
||||
{
|
||||
Abc_Obj_t * pNode;
|
||||
int i, Counter;
|
||||
assert( !Abc_NtkIsStrash(pNtk) );
|
||||
// mark the nodes reachable from the POs
|
||||
for ( i = 0; i < vNodes->nSize; i++ )
|
||||
{
|
||||
pNode = vNodes->pArray[i];
|
||||
assert( Abc_ObjIsNode(pNode) );
|
||||
pNode->fMarkA = 1;
|
||||
}
|
||||
Vec_PtrFree( vNodes );
|
||||
// if it is an AIG, also mark the constant 1 node
|
||||
if ( Abc_NtkConst1(pNtk) )
|
||||
Abc_NtkConst1(pNtk)->fMarkA = 1;
|
||||
|
|
@ -472,14 +495,9 @@ int Abc_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose )
|
|||
// unmark the remaining nodes
|
||||
Abc_NtkForEachNode( pNtk, pNode, i )
|
||||
pNode->fMarkA = 0;
|
||||
if ( fVerbose )
|
||||
printf( "Cleanup removed %d dangling nodes.\n", Counter );
|
||||
// check
|
||||
if ( !Abc_NtkCheck( pNtk ) )
|
||||
{
|
||||
printf( "Abc_NtkCleanup: The network check has failed.\n" );
|
||||
return -1;
|
||||
}
|
||||
return Counter;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -79,6 +79,8 @@ extern void Seq_NtkLatchGetInitNums( Abc_Ntk_t * pNtk, int * pInits )
|
|||
extern int Seq_NtkLatchGetEqualFaninNum( Abc_Ntk_t * pNtk );
|
||||
extern int Seq_NtkCountNodesAboveLimit( Abc_Ntk_t * pNtk, int Limit );
|
||||
extern int Seq_MapComputeAreaFlows( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern Vec_Ptr_t * Seq_NtkReachNodes( Abc_Ntk_t * pNtk, int fFromPos );
|
||||
extern int Seq_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
|
|
|
|||
|
|
@ -73,7 +73,8 @@ void Seq_NtkSeqRetimeDelay( Abc_Ntk_t * pNtk, int nMaxIters, int fInitial, int f
|
|||
Seq_NtkLatchSetValues( pNtk, ABC_INIT_DC );
|
||||
// get the retiming lags
|
||||
p->nMaxIters = nMaxIters;
|
||||
Seq_AigRetimeDelayLags( pNtk, fVerbose );
|
||||
if ( !Seq_AigRetimeDelayLags( pNtk, fVerbose ) )
|
||||
return;
|
||||
// implement this retiming
|
||||
RetValue = Seq_NtkImplementRetiming( pNtk, p->vLags, fVerbose );
|
||||
if ( RetValue == 0 )
|
||||
|
|
|
|||
|
|
@ -44,11 +44,11 @@ static int Seq_RetimeNodeUpdateLValue( Abc_Obj_t * pObj, int Fi );
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
int Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p = pNtk->pManFunc;
|
||||
Abc_Obj_t * pNode;
|
||||
int i, FiMax, FiBest, RetValue;
|
||||
int i, FiMax, FiBest, RetValue, clk, clkIter;
|
||||
char NodeLag;
|
||||
|
||||
assert( Abc_NtkIsSeq( pNtk ) );
|
||||
|
|
@ -57,15 +57,29 @@ void Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
|
|||
FiMax = 2 + Seq_NtkLevelMax(pNtk);
|
||||
|
||||
// make sure this clock period is feasible
|
||||
assert( Seq_RetimeForPeriod( pNtk, FiMax, fVerbose ) );
|
||||
if ( !Seq_RetimeForPeriod( pNtk, FiMax, fVerbose ) )
|
||||
{
|
||||
Vec_StrFill( p->vLags, p->nSize, 0 );
|
||||
printf( "Error: The upper bound on the clock period cannot be computed.\n" );
|
||||
printf( "The reason for this error may be the presence in the circuit of logic\n" );
|
||||
printf( "that is not reachable from the PIs. Mapping/retiming is not performed.\n" );
|
||||
return 0;
|
||||
}
|
||||
|
||||
// search for the optimal clock period between 0 and nLevelMax
|
||||
clk = clock();
|
||||
FiBest = Seq_RetimeSearch_rec( pNtk, 0, FiMax, fVerbose );
|
||||
clkIter = clock() - clk;
|
||||
|
||||
// recompute the best l-values
|
||||
RetValue = Seq_RetimeForPeriod( pNtk, FiBest, fVerbose );
|
||||
assert( RetValue );
|
||||
|
||||
// fix the problem with non-converged delays
|
||||
Abc_AigForEachAnd( pNtk, pNode, i )
|
||||
if ( Seq_NodeGetLValue(pNode) < -ABC_INFINITY/2 )
|
||||
Seq_NodeSetLValue( pNode, 0 );
|
||||
|
||||
// write the retiming lags
|
||||
Vec_StrFill( p->vLags, p->nSize, 0 );
|
||||
Abc_AigForEachAnd( pNtk, pNode, i )
|
||||
|
|
@ -73,39 +87,39 @@ void Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
|
|||
NodeLag = Seq_NodeComputeLag( Seq_NodeGetLValue(pNode), FiBest );
|
||||
Seq_NodeSetLag( pNode, NodeLag );
|
||||
}
|
||||
/*
|
||||
{
|
||||
Abc_Obj_t * pFanin, * pFanout;
|
||||
pNode = Abc_NtkObj( pNtk, 823 );
|
||||
printf( "Node %d. Lag = %d. LValue = %d. Latches = (%d,%d) (%d,%d).\n", pNode->Id, Seq_NodeGetLag(pNode), Seq_NodeGetLValue(pNode),
|
||||
Seq_ObjFaninL0(pNode), Seq_ObjFaninL1(pNode), Seq_ObjFanoutL(pNode, Abc_NtkObj(pNtk, 826)), Seq_ObjFanoutL(pNode, Abc_NtkObj(pNtk, 1210)) );
|
||||
pFanin = Abc_ObjFanin0( pNode );
|
||||
printf( "Fanin %d. Lag = %d. LValue = %d. Latches = (%d,%d)\n", pFanin->Id, Seq_NodeGetLag(pFanin), Seq_NodeGetLValue(pFanin),
|
||||
Seq_ObjFaninL0(pFanin), Seq_ObjFaninL1(pFanin) );
|
||||
pFanin = Abc_ObjFanin1( pNode );
|
||||
printf( "Fanin %d. Lag = %d. LValue = %d.\n", pFanin->Id, Seq_NodeGetLag(pFanin), Seq_NodeGetLValue(pFanin) );
|
||||
Abc_ObjForEachFanout( pNode, pFanout, i )
|
||||
printf( "Fanout %d. Lag = %d. LValue = %d.\n", pFanout->Id, Seq_NodeGetLag(pFanout), Seq_NodeGetLValue(pFanout) );
|
||||
Abc_ObjForEachFanout( Abc_ObjFanin0(pNode), pFanout, i )
|
||||
printf( "Fanout %d. Lag = %d. LValue = %d.\n", pFanout->Id, Seq_NodeGetLag(pFanout), Seq_NodeGetLValue(pFanout) );
|
||||
}
|
||||
*/
|
||||
|
||||
// print the result
|
||||
if ( fVerbose )
|
||||
printf( "The best clock period is %3d.\n", FiBest );
|
||||
|
||||
/*
|
||||
printf( "LValues : " );
|
||||
printf( "lvalues and lags : " );
|
||||
Abc_AigForEachAnd( pNtk, pNode, i )
|
||||
printf( "%d=%d ", i, Seq_NodeGetLValue(pNode) );
|
||||
printf( "\n" );
|
||||
printf( "Lags : " );
|
||||
Abc_AigForEachAnd( pNtk, pNode, i )
|
||||
if ( Vec_StrEntry(p->vLags,i) != 0 )
|
||||
printf( "%d=%d(%d)(%d) ", i, Vec_StrEntry(p->vLags,i), Seq_NodeGetLValue(pNode), Seq_NodeGetLValue(pNode) - FiBest * Vec_StrEntry(p->vLags,i) );
|
||||
printf( "%d=%d(%d) ", pNode->Id, Seq_NodeGetLValue(pNode), Seq_NodeGetLag(pNode) );
|
||||
printf( "\n" );
|
||||
*/
|
||||
/*
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%d ", FiBest );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
/*
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%.2f ", (float)(p->timeCuts)/(float)(CLOCKS_PER_SEC) );
|
||||
fprintf( pTable, "%.2f ", (float)(clkIter)/(float)(CLOCKS_PER_SEC) );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
|
@ -203,6 +217,14 @@ int Seq_RetimeForPeriod( Abc_Ntk_t * pNtk, int Fi, int fVerbose )
|
|||
else
|
||||
printf( "Period = %3d. Iterations = %3d. Updates = %10d. Feasible\n", Fi, c, Counter );
|
||||
}
|
||||
/*
|
||||
// check if any AND gates have infinite delay
|
||||
Counter = 0;
|
||||
Abc_AigForEachAnd( pNtk, pObj, i )
|
||||
Counter += (Seq_NodeGetLValue(pObj) < -ABC_INFINITY/2);
|
||||
if ( Counter > 0 )
|
||||
printf( "Warning: %d internal nodes have wrong l-values!\n", Counter );
|
||||
*/
|
||||
return RetValue != SEQ_UPDATE_FAIL;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -62,7 +62,8 @@ Abc_Ntk_t * Seq_NtkFpgaMapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose
|
|||
p->nMaxIters = nMaxIters;
|
||||
|
||||
// find the best mapping and retiming for all nodes (p->vLValues, p->vBestCuts, p->vLags)
|
||||
Seq_FpgaMappingDelays( pNtk, fVerbose );
|
||||
if ( !Seq_FpgaMappingDelays( pNtk, fVerbose ) )
|
||||
return NULL;
|
||||
if ( RetValue = Abc_NtkGetChoiceNum(pNtk) )
|
||||
{
|
||||
printf( "The network has %d choices. Deriving the resulting network is skipped.\n", RetValue );
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ extern Cut_Man_t * Abc_NtkCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams );
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
int Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p = pNtk->pManFunc;
|
||||
Cut_Params_t Params, * pParams = &Params;
|
||||
|
|
@ -78,8 +78,9 @@ p->timeCuts = clock() - clk;
|
|||
|
||||
// compute the delays
|
||||
clk = clock();
|
||||
Seq_AigRetimeDelayLags( pNtk, fVerbose );
|
||||
p->timeDelay = clock() - clk;
|
||||
if ( !Seq_AigRetimeDelayLags( pNtk, fVerbose ) )
|
||||
return 0;
|
||||
p->timeDelay = clock() - clk;
|
||||
|
||||
// collect the nodes and cuts used in the mapping
|
||||
p->vMapAnds = Vec_PtrAlloc( 1000 );
|
||||
|
|
@ -94,6 +95,7 @@ p->timeDelay = clock() - clk;
|
|||
// remove the cuts
|
||||
Cut_ManStop( p->pCutMan );
|
||||
p->pCutMan = NULL;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
|
@ -161,7 +163,7 @@ Cut_Cut_t * Seq_FpgaMappingSelectCut( Abc_Obj_t * pAnd )
|
|||
for ( pCut = pList->pNext; pCut; pCut = pCut->pNext )
|
||||
{
|
||||
ArrivalCut = *((int *)&pCut->uSign);
|
||||
assert( ArrivalCut >= ArrivalMin );
|
||||
// assert( ArrivalCut >= ArrivalMin );
|
||||
if ( ArrivalCut > ArrivalMin )
|
||||
continue;
|
||||
CostCur = 0.0;
|
||||
|
|
|
|||
|
|
@ -217,15 +217,15 @@ static inline void Seq_NodeSetInitOne( Abc_Obj_t * pObj, int Edge, int
|
|||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/*=== seqAigIter.c =============================================================*/
|
||||
extern void Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Seq_AigRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Seq_NtkImplementRetiming( Abc_Ntk_t * pNtk, Vec_Str_t * vLags, int fVerbose );
|
||||
/*=== seqFpgaIter.c ============================================================*/
|
||||
extern void Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Seq_FpgaMappingDelays( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Seq_FpgaNodeUpdateLValue( Abc_Obj_t * pObj, int Fi );
|
||||
/*=== seqMapIter.c ============================================================*/
|
||||
extern void Seq_MapRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Seq_MapRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
/*=== seqRetIter.c =============================================================*/
|
||||
extern void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose );
|
||||
/*=== seqLatch.c ===============================================================*/
|
||||
extern void Seq_NodeInsertFirst( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init );
|
||||
extern void Seq_NodeInsertLast( Abc_Obj_t * pObj, int Edge, Abc_InitType_t Init );
|
||||
|
|
|
|||
|
|
@ -74,12 +74,14 @@ Abc_Ntk_t * Seq_MapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose )
|
|||
p->fStandCells = 1;
|
||||
|
||||
// find the best mapping and retiming for all nodes (p->vLValues, p->vBestCuts, p->vLags)
|
||||
Seq_MapRetimeDelayLags( pNtk, fVerbose );
|
||||
if ( !Seq_MapRetimeDelayLags( pNtk, fVerbose ) )
|
||||
return NULL;
|
||||
if ( RetValue = Abc_NtkGetChoiceNum(pNtk) )
|
||||
{
|
||||
printf( "The network has %d choices. Deriving the resulting network is skipped.\n", RetValue );
|
||||
return NULL;
|
||||
}
|
||||
return NULL;
|
||||
|
||||
// duplicate the nodes contained in multiple cuts
|
||||
pNtkNew = Seq_NtkMapDup( pNtk );
|
||||
|
|
|
|||
|
|
@ -1,361 +0,0 @@
|
|||
/**CFile****************************************************************
|
||||
|
||||
FileName [seqMapCore.c]
|
||||
|
||||
SystemName [ABC: Logic synthesis and verification system.]
|
||||
|
||||
PackageName [Construction and manipulation of sequential AIGs.]
|
||||
|
||||
Synopsis [The core of SC mapping/retiming package.]
|
||||
|
||||
Author [Alan Mishchenko]
|
||||
|
||||
Affiliation [UC Berkeley]
|
||||
|
||||
Date [Ver. 1.0. Started - June 20, 2005.]
|
||||
|
||||
Revision [$Id: seqMapCore.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
|
||||
|
||||
***********************************************************************/
|
||||
|
||||
#include "seqInt.h"
|
||||
#include "main.h"
|
||||
#include "mio.h"
|
||||
#include "mapper.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// DECLARATIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
extern Abc_Ntk_t * Seq_NtkMapDup( Abc_Ntk_t * pNtk );
|
||||
extern int Seq_NtkMapInitCompatible( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
extern Abc_Ntk_t * Seq_NtkSeqMapMapped( Abc_Ntk_t * pNtk );
|
||||
|
||||
static int Seq_MapMappingCount( Abc_Ntk_t * pNtk );
|
||||
static int Seq_MapMappingCount_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Vec_Ptr_t * vLeaves );
|
||||
static Abc_Obj_t * Seq_MapMappingBuild_rec( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk, unsigned SeqEdge, int fTop, int fCompl, int LagCut, Vec_Ptr_t * vLeaves, unsigned uPhase );
|
||||
static DdNode * Seq_MapMappingBdd_rec( DdManager * dd, Abc_Ntk_t * pNtk, unsigned SeqEdge, Vec_Ptr_t * vLeaves );
|
||||
static void Seq_MapMappingEdges_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Abc_Obj_t * pPrev, Vec_Ptr_t * vLeaves, Vec_Vec_t * vMapEdges );
|
||||
static void Seq_MapMappingConnect_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Abc_Obj_t * pPrev, int Edge, Abc_Obj_t * pRoot, Vec_Ptr_t * vLeaves );
|
||||
static DdNode * Seq_MapMappingConnectBdd_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Abc_Obj_t * pPrev, int Edge, Abc_Obj_t * pRoot, Vec_Ptr_t * vLeaves );
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// FUNCTION DEFINITIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Performs Map mapping and retiming.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Seq_MapRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p = pNtk->pManFunc;
|
||||
Abc_Ntk_t * pNtkNew;
|
||||
Abc_Ntk_t * pNtkMap;
|
||||
int RetValue;
|
||||
|
||||
// derive the supergate library
|
||||
if ( Abc_FrameReadLibSuper() == NULL && Abc_FrameReadLibGen() )
|
||||
{
|
||||
printf( "A simple supergate library is derived from gate library \"%s\".\n",
|
||||
Mio_LibraryReadName(Abc_FrameReadLibGen()) );
|
||||
Map_SuperLibDeriveFromGenlib( Abc_FrameReadLibGen() );
|
||||
}
|
||||
p->pSuperLib = Abc_FrameReadLibSuper();
|
||||
p->nVarsMax = Map_SuperLibReadVarsMax(p->pSuperLib);
|
||||
p->nMaxIters = nMaxIters;
|
||||
p->fStandCells = 1;
|
||||
|
||||
// find the best mapping and retiming for all nodes (p->vLValues, p->vBestCuts, p->vLags)
|
||||
Seq_MapRetimeDelayLags( pNtk, fVerbose );
|
||||
if ( RetValue = Abc_NtkGetChoiceNum(pNtk) )
|
||||
{
|
||||
printf( "The network has %d choices. Deriving the resulting network is skipped.\n", RetValue );
|
||||
return NULL;
|
||||
}
|
||||
|
||||
// duplicate the nodes contained in multiple cuts
|
||||
pNtkNew = Seq_NtkMapDup( pNtk );
|
||||
return pNtkNew;
|
||||
|
||||
// implement the retiming
|
||||
RetValue = Seq_NtkImplementRetiming( pNtkNew, ((Abc_Seq_t *)pNtkNew->pManFunc)->vLags, fVerbose );
|
||||
if ( RetValue == 0 )
|
||||
printf( "Retiming completed but initial state computation has failed.\n" );
|
||||
// return pNtkNew;
|
||||
|
||||
// check the compatibility of initial states computed
|
||||
if ( RetValue = Seq_NtkMapInitCompatible( pNtkNew, fVerbose ) )
|
||||
{
|
||||
printf( "The number of LUTs with incompatible edges = %d.\n", RetValue );
|
||||
Abc_NtkDelete( pNtkNew );
|
||||
return NULL;
|
||||
}
|
||||
|
||||
// create the final mapped network
|
||||
pNtkMap = Seq_NtkSeqMapMapped( pNtkNew );
|
||||
Abc_NtkDelete( pNtkNew );
|
||||
return pNtkMap;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Derives the network by duplicating some of the nodes.]
|
||||
|
||||
Description [Information about mapping is given as mapping nodes (p->vMapAnds)
|
||||
and best cuts for each node (p->vMapCuts).]
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Seq_NtkMapDup( Abc_Ntk_t * pNtk )
|
||||
{
|
||||
Abc_Seq_t * pNew, * p = pNtk->pManFunc;
|
||||
Seq_Match_t * pMatch;
|
||||
Abc_Ntk_t * pNtkNew;
|
||||
Abc_Obj_t * pObj, * pFanin, * pFaninNew, * pLeaf;
|
||||
Vec_Ptr_t * vLeaves;
|
||||
unsigned SeqEdge;
|
||||
int i, k, nObjsNew, Lag;
|
||||
|
||||
assert( Abc_NtkIsSeq(pNtk) );
|
||||
|
||||
// start the expanded network
|
||||
pNtkNew = Abc_NtkStartFrom( pNtk, pNtk->ntkType, pNtk->ntkFunc );
|
||||
Abc_NtkCleanNext(pNtk);
|
||||
|
||||
// start the new sequential AIG manager
|
||||
nObjsNew = 1 + Abc_NtkPiNum(pNtk) + Abc_NtkPoNum(pNtk) + Seq_MapMappingCount(pNtk);
|
||||
Seq_Resize( pNtkNew->pManFunc, nObjsNew );
|
||||
|
||||
// duplicate the nodes in the mapping
|
||||
Vec_PtrForEachEntry( p->vMapAnds, pMatch, i )
|
||||
{
|
||||
// Abc_NtkDupObj( pNtkNew, pMatch->pAnd );
|
||||
if ( !pMatch->fCompl )
|
||||
pMatch->pAnd->pCopy = Abc_NtkCreateNode( pNtkNew );
|
||||
else
|
||||
pMatch->pAnd->pNext = Abc_NtkCreateNode( pNtkNew );
|
||||
}
|
||||
|
||||
// recursively construct the internals of each node
|
||||
Vec_PtrForEachEntry( p->vMapAnds, pMatch, i )
|
||||
{
|
||||
vLeaves = Vec_VecEntry( p->vMapCuts, i );
|
||||
Seq_MapMappingBuild_rec( pNtkNew, pNtk, pMatch->pAnd->Id << 8, 1, pMatch->fCompl, Seq_NodeGetLag(pMatch->pAnd), vLeaves, pMatch->uPhase );
|
||||
}
|
||||
assert( nObjsNew == pNtkNew->nObjs );
|
||||
|
||||
// set the POs
|
||||
// Abc_NtkFinalize( pNtk, pNtkNew );
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
{
|
||||
pFanin = Abc_ObjFanin0(pObj);
|
||||
if ( Abc_ObjFaninC0(pObj) )
|
||||
pFaninNew = pFanin->pNext ? pFanin->pNext : Abc_ObjNot(pFanin->pCopy);
|
||||
else
|
||||
pFaninNew = pFanin->pCopy ? pFanin->pCopy : Abc_ObjNot(pFanin->pNext);
|
||||
Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
|
||||
}
|
||||
|
||||
// duplicate the latches on the PO edges
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
Seq_NodeDupLats( pObj->pCopy, pObj, 0 );
|
||||
|
||||
// transfer the mapping info to the new manager
|
||||
Vec_PtrForEachEntry( p->vMapAnds, pMatch, i )
|
||||
{
|
||||
// get the leaves of the cut
|
||||
vLeaves = Vec_VecEntry( p->vMapCuts, i );
|
||||
// convert the leaf nodes
|
||||
Vec_PtrForEachEntry( vLeaves, pLeaf, k )
|
||||
{
|
||||
SeqEdge = (unsigned)pLeaf;
|
||||
pLeaf = Abc_NtkObj( pNtk, SeqEdge >> 8 );
|
||||
Lag = (SeqEdge & 255) + Seq_NodeGetLag(pMatch->pAnd) - Seq_NodeGetLag(pLeaf);
|
||||
assert( Lag >= 0 );
|
||||
// translate the old leaf into the leaf in the new network
|
||||
// Vec_PtrWriteEntry( vLeaves, k, (void *)((pLeaf->pCopy->Id << 8) | Lag) );
|
||||
|
||||
// printf( "%d -> %d\n", pLeaf->Id, pLeaf->pCopy->Id );
|
||||
}
|
||||
// convert the root node
|
||||
// Vec_PtrWriteEntry( p->vMapAnds, i, pObj->pCopy );
|
||||
pMatch->pAnd = pMatch->pAnd->pCopy;
|
||||
}
|
||||
pNew = pNtkNew->pManFunc;
|
||||
pNew->nVarsMax = p->nVarsMax;
|
||||
pNew->vMapAnds = p->vMapAnds; p->vMapAnds = NULL;
|
||||
pNew->vMapCuts = p->vMapCuts; p->vMapCuts = NULL;
|
||||
|
||||
if ( !Abc_NtkCheck( pNtkNew ) )
|
||||
fprintf( stdout, "Seq_NtkMapDup(): Network check has failed.\n" );
|
||||
return pNtkNew;
|
||||
}
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Checks if the initial states are compatible.]
|
||||
|
||||
Description [Checks of all the initial states on the fanins edges
|
||||
of the cut have compatible number of latches and initial states.
|
||||
If this is not true, then the mapped network with the does not have initial
|
||||
state. Returns the number of LUTs with incompatible edges.]
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Seq_NtkMapInitCompatible( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Derives the final mapped network.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Seq_NtkSeqMapMapped( Abc_Ntk_t * pNtk )
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Counts the number of nodes in the bag.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Seq_MapMappingCount( Abc_Ntk_t * pNtk )
|
||||
{
|
||||
Abc_Seq_t * p = pNtk->pManFunc;
|
||||
Vec_Ptr_t * vLeaves;
|
||||
Seq_Match_t * pMatch;
|
||||
int i, Counter = 0;
|
||||
Vec_PtrForEachEntry( p->vMapAnds, pMatch, i )
|
||||
{
|
||||
vLeaves = Vec_VecEntry( p->vMapCuts, i );
|
||||
Counter += Seq_MapMappingCount_rec( pNtk, pMatch->pAnd->Id << 8, vLeaves );
|
||||
}
|
||||
return Counter;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Counts the number of nodes in the bag.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Seq_MapMappingCount_rec( Abc_Ntk_t * pNtk, unsigned SeqEdge, Vec_Ptr_t * vLeaves )
|
||||
{
|
||||
Abc_Obj_t * pObj, * pLeaf;
|
||||
unsigned SeqEdge0, SeqEdge1;
|
||||
int Lag, i;
|
||||
// get the object and the lag
|
||||
pObj = Abc_NtkObj( pNtk, SeqEdge >> 8 );
|
||||
Lag = SeqEdge & 255;
|
||||
// if the node is the fanin of the cut, return
|
||||
Vec_PtrForEachEntry( vLeaves, pLeaf, i )
|
||||
if ( SeqEdge == (unsigned)pLeaf )
|
||||
return 0;
|
||||
// continue unfolding
|
||||
assert( Abc_NodeIsAigAnd(pObj) );
|
||||
// get new sequential edges
|
||||
assert( Lag + Seq_ObjFaninL0(pObj) < 255 );
|
||||
assert( Lag + Seq_ObjFaninL1(pObj) < 255 );
|
||||
SeqEdge0 = (Abc_ObjFanin0(pObj)->Id << 8) + Lag + Seq_ObjFaninL0(pObj);
|
||||
SeqEdge1 = (Abc_ObjFanin1(pObj)->Id << 8) + Lag + Seq_ObjFaninL1(pObj);
|
||||
// call for the children
|
||||
return 1 + Seq_MapMappingCount_rec( pNtk, SeqEdge0, vLeaves ) +
|
||||
Seq_MapMappingCount_rec( pNtk, SeqEdge1, vLeaves );
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Collects the edges pointing to the leaves of the cut.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Obj_t * Seq_MapMappingBuild_rec( Abc_Ntk_t * pNtkNew, Abc_Ntk_t * pNtk, unsigned SeqEdge, int fTop, int fCompl, int LagCut, Vec_Ptr_t * vLeaves, unsigned uPhase )
|
||||
{
|
||||
Abc_Obj_t * pObj, * pObjNew, * pLeaf, * pFaninNew0, * pFaninNew1;
|
||||
unsigned SeqEdge0, SeqEdge1;
|
||||
int Lag, i;
|
||||
// get the object and the lag
|
||||
pObj = Abc_NtkObj( pNtk, SeqEdge >> 8 );
|
||||
Lag = SeqEdge & 255;
|
||||
// if the node is the fanin of the cut, return
|
||||
Vec_PtrForEachEntry( vLeaves, pLeaf, i )
|
||||
if ( SeqEdge == (unsigned)pLeaf )
|
||||
{
|
||||
// if ( uPhase & (1 << i) ) // negative phase is required
|
||||
// return pObj->pNext? pObj->pNext : Abc_ObjNot(pObj->pCopy);
|
||||
// else // positive phase is required
|
||||
// return pObj->pCopy? pObj->pCopy : Abc_ObjNot(pObj->pNext);
|
||||
return pObj->pCopy? pObj->pCopy : Abc_ObjNot(pObj->pNext);
|
||||
}
|
||||
// continue unfolding
|
||||
assert( Abc_NodeIsAigAnd(pObj) );
|
||||
// get new sequential edges
|
||||
assert( Lag + Seq_ObjFaninL0(pObj) < 255 );
|
||||
assert( Lag + Seq_ObjFaninL1(pObj) < 255 );
|
||||
SeqEdge0 = (Abc_ObjFanin0(pObj)->Id << 8) + Lag + Seq_ObjFaninL0(pObj);
|
||||
SeqEdge1 = (Abc_ObjFanin1(pObj)->Id << 8) + Lag + Seq_ObjFaninL1(pObj);
|
||||
// call for the children
|
||||
pObjNew = fTop? (fCompl? pObj->pNext : pObj->pCopy) : Abc_NtkCreateNode( pNtkNew );
|
||||
// solve subproblems
|
||||
pFaninNew0 = Seq_MapMappingBuild_rec( pNtkNew, pNtk, SeqEdge0, 0, fCompl, LagCut, vLeaves, uPhase );
|
||||
pFaninNew1 = Seq_MapMappingBuild_rec( pNtkNew, pNtk, SeqEdge1, 0, fCompl, LagCut, vLeaves, uPhase );
|
||||
// add the fanins to the node
|
||||
Abc_ObjAddFanin( pObjNew, Abc_ObjNotCond( pFaninNew0, Abc_ObjFaninC0(pObj) ) );
|
||||
Abc_ObjAddFanin( pObjNew, Abc_ObjNotCond( pFaninNew1, Abc_ObjFaninC1(pObj) ) );
|
||||
Seq_NodeDupLats( pObjNew, pObj, 0 );
|
||||
Seq_NodeDupLats( pObjNew, pObj, 1 );
|
||||
// set the lag of the new node equal to the internal lag plus mapping/retiming lag
|
||||
Seq_NodeSetLag( pObjNew, (char)(Lag + LagCut) );
|
||||
// Seq_NodeSetLag( pObjNew, (char)(Lag) );
|
||||
return pObjNew;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
|
@ -48,7 +48,7 @@ extern Cut_Man_t * Abc_NtkSeqCuts( Abc_Ntk_t * pNtk, Cut_Params_t * pParams );
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_MapRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
int Seq_MapRetimeDelayLags( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p = pNtk->pManFunc;
|
||||
Cut_Params_t Params, * pParams = &Params;
|
||||
|
|
@ -81,8 +81,21 @@ p->timeCuts = clock() - clk;
|
|||
// compute the delays
|
||||
clk = clock();
|
||||
FiBest = Seq_MapRetimeDelayLagsInternal( pNtk, fVerbose );
|
||||
if ( FiBest == 0.0 )
|
||||
return 0;
|
||||
p->timeDelay = clock() - clk;
|
||||
|
||||
/*
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%.2f ", FiBest );
|
||||
fprintf( pTable, "%.2f ", (float)(p->timeCuts)/(float)(CLOCKS_PER_SEC) );
|
||||
fprintf( pTable, "%.2f ", (float)(p->timeDelay)/(float)(CLOCKS_PER_SEC) );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
// clean the marks
|
||||
Abc_NtkForEachObj( pNtk, pObj, i )
|
||||
assert( !pObj->fMarkA && !pObj->fMarkB );
|
||||
|
|
@ -104,6 +117,7 @@ p->timeDelay = clock() - clk;
|
|||
// remove the cuts
|
||||
Cut_ManStop( p->pCutMan );
|
||||
p->pCutMan = NULL;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
|
@ -144,7 +158,15 @@ float Seq_MapRetimeDelayLagsInternal( Abc_Ntk_t * pNtk, int fVerbose )
|
|||
Delta /= 2;
|
||||
|
||||
// make sure this clock period is feasible
|
||||
assert( Seq_MapRetimeForPeriod( pNtk, FiMax, fVerbose ) );
|
||||
if ( !Seq_MapRetimeForPeriod( pNtk, FiMax, fVerbose ) )
|
||||
{
|
||||
Vec_StrFill( p->vLags, p->nSize, 0 );
|
||||
Vec_StrFill( p->vLagsN, p->nSize, 0 );
|
||||
printf( "Error: The upper bound on the clock period cannot be computed.\n" );
|
||||
printf( "The reason for this error may be the presence in the circuit of logic\n" );
|
||||
printf( "that is not reachable from the PIs. Mapping/retiming is not performed.\n" );
|
||||
return 0;
|
||||
}
|
||||
|
||||
// search for the optimal clock period between 0 and nLevelMax
|
||||
FiBest = Seq_MapRetimeSearch_rec( pNtk, 0.0, FiMax, Delta, fVerbose );
|
||||
|
|
@ -153,6 +175,15 @@ float Seq_MapRetimeDelayLagsInternal( Abc_Ntk_t * pNtk, int fVerbose )
|
|||
RetValue = Seq_MapRetimeForPeriod( pNtk, FiBest, fVerbose );
|
||||
assert( RetValue );
|
||||
|
||||
// fix the problem with non-converged delays
|
||||
Abc_AigForEachAnd( pNtk, pNode, i )
|
||||
{
|
||||
if ( Seq_NodeGetLValueP(pNode) < -ABC_INFINITY/2 )
|
||||
Seq_NodeSetLValueP( pNode, 0 );
|
||||
if ( Seq_NodeGetLValueN(pNode) < -ABC_INFINITY/2 )
|
||||
Seq_NodeSetLValueN( pNode, 0 );
|
||||
}
|
||||
|
||||
// write the retiming lags for both phases of each node
|
||||
Vec_StrFill( p->vLags, p->nSize, 0 );
|
||||
Vec_StrFill( p->vLagsN, p->nSize, 0 );
|
||||
|
|
@ -579,6 +610,8 @@ void Seq_MapCanonicizeTruthTables( Abc_Ntk_t * pNtk )
|
|||
Abc_AigForEachAnd( pNtk, pObj, i )
|
||||
{
|
||||
pList = Abc_NodeReadCuts( Seq_NodeCutMan(pObj), pObj );
|
||||
if ( pList == NULL )
|
||||
continue;
|
||||
for ( pCut = pList->pNext; pCut; pCut = pCut->pNext )
|
||||
Cut_TruthCanonicize( pCut );
|
||||
}
|
||||
|
|
|
|||
|
|
@ -60,7 +60,11 @@ Abc_Ntk_t * Seq_NtkRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fInitial, int fV
|
|||
if ( !fInitial )
|
||||
Seq_NtkLatchSetValues( pNtkSeq, ABC_INIT_DC );
|
||||
// find the best mapping and retiming
|
||||
Seq_NtkRetimeDelayLags( pNtk, pNtkSeq, fVerbose );
|
||||
if ( !Seq_NtkRetimeDelayLags( pNtk, pNtkSeq, fVerbose ) )
|
||||
return NULL;
|
||||
return NULL;
|
||||
|
||||
|
||||
// implement the retiming
|
||||
RetValue = Seq_NtkImplementRetiming( pNtkSeq, p->vLags, fVerbose );
|
||||
if ( RetValue == 0 )
|
||||
|
|
|
|||
|
|
@ -1,453 +0,0 @@
|
|||
/**CFile****************************************************************
|
||||
|
||||
FileName [seqRetCore.c]
|
||||
|
||||
SystemName [ABC: Logic synthesis and verification system.]
|
||||
|
||||
PackageName [Construction and manipulation of sequential AIGs.]
|
||||
|
||||
Synopsis [The core of FPGA mapping/retiming package.]
|
||||
|
||||
Author [Alan Mishchenko]
|
||||
|
||||
Affiliation [UC Berkeley]
|
||||
|
||||
Date [Ver. 1.0. Started - June 20, 2005.]
|
||||
|
||||
Revision [$Id: seqRetCore.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
|
||||
|
||||
***********************************************************************/
|
||||
|
||||
#include "seqInt.h"
|
||||
#include "dec.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// DECLARATIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
static Abc_Ntk_t * Seq_NtkRetimeDerive( Abc_Ntk_t * pNtk, int fVerbose );
|
||||
static Abc_Obj_t * Seq_NodeRetimeDerive( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pNode, char * pSop );
|
||||
static void Seq_NodeAddEdges_rec( Abc_Obj_t * pGoal, Abc_Obj_t * pNode, Abc_InitType_t Init );
|
||||
static Abc_Ntk_t * Seq_NtkRetimeReconstruct( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkSeq );
|
||||
static Abc_Obj_t * Seq_EdgeReconstruct_rec( Abc_Obj_t * pGoal, Abc_Obj_t * pNode );
|
||||
static Abc_Obj_t * Seq_EdgeReconstructPO( Abc_Obj_t * pNode );
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// FUNCTION DEFINITIONS ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Performs FPGA mapping and retiming.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Seq_NtkRetime( Abc_Ntk_t * pNtk, int nMaxIters, int fInitial, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p;
|
||||
Abc_Ntk_t * pNtkSeq, * pNtkNew;
|
||||
int RetValue;
|
||||
assert( !Abc_NtkHasAig(pNtk) );
|
||||
// derive the isomorphic seq AIG
|
||||
pNtkSeq = Seq_NtkRetimeDerive( pNtk, fVerbose );
|
||||
p = pNtkSeq->pManFunc;
|
||||
p->nMaxIters = nMaxIters;
|
||||
|
||||
if ( !fInitial )
|
||||
Seq_NtkLatchSetValues( pNtkSeq, ABC_INIT_DC );
|
||||
// find the best mapping and retiming
|
||||
Seq_NtkRetimeDelayLags( pNtk, pNtkSeq, fVerbose );
|
||||
// implement the retiming
|
||||
RetValue = Seq_NtkImplementRetiming( pNtkSeq, p->vLags, fVerbose );
|
||||
if ( RetValue == 0 )
|
||||
printf( "Retiming completed but initial state computation has failed.\n" );
|
||||
|
||||
//return pNtkSeq;
|
||||
|
||||
// create the final mapped network
|
||||
pNtkNew = Seq_NtkRetimeReconstruct( pNtk, pNtkSeq );
|
||||
Abc_NtkDelete( pNtkSeq );
|
||||
return pNtkNew;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Derives the isomorphic seq AIG.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Seq_NtkRetimeDerive( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p;
|
||||
Abc_Ntk_t * pNtkNew;
|
||||
Abc_Obj_t * pObj, * pFanin, * pFanout;
|
||||
int i, k, RetValue, fHasBdds;
|
||||
char * pSop;
|
||||
|
||||
// make sure it is an AIG without self-feeding latches
|
||||
assert( !Abc_NtkHasAig(pNtk) );
|
||||
if ( RetValue = Abc_NtkRemoveSelfFeedLatches(pNtk) )
|
||||
printf( "Modified %d self-feeding latches. The result will not verify.\n", RetValue );
|
||||
assert( Abc_NtkCountSelfFeedLatches(pNtk) == 0 );
|
||||
|
||||
// remove the dangling nodes
|
||||
Abc_NtkCleanup( pNtk, fVerbose );
|
||||
|
||||
// transform logic functions from BDD to SOP
|
||||
if ( fHasBdds = Abc_NtkIsBddLogic(pNtk) )
|
||||
Abc_NtkBddToSop(pNtk);
|
||||
|
||||
// start the network
|
||||
pNtkNew = Abc_NtkAlloc( ABC_NTK_SEQ, ABC_FUNC_AIG );
|
||||
// duplicate the name and the spec
|
||||
pNtkNew->pName = util_strsav(pNtk->pName);
|
||||
pNtkNew->pSpec = util_strsav(pNtk->pSpec);
|
||||
|
||||
// map the constant nodes
|
||||
Abc_NtkCleanCopy( pNtk );
|
||||
// clone the PIs/POs/latches
|
||||
Abc_NtkForEachPi( pNtk, pObj, i )
|
||||
Abc_NtkDupObj( pNtkNew, pObj );
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
Abc_NtkDupObj( pNtkNew, pObj );
|
||||
// copy the names
|
||||
Abc_NtkForEachPi( pNtk, pObj, i )
|
||||
Abc_NtkLogicStoreName( pObj->pCopy, Abc_ObjName(pObj) );
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
Abc_NtkLogicStoreName( pObj->pCopy, Abc_ObjName(pObj) );
|
||||
|
||||
// create one AND for each logic node
|
||||
Abc_NtkForEachNode( pNtk, pObj, i )
|
||||
{
|
||||
if ( Abc_ObjFaninNum(pObj) == 0 && Abc_ObjFanoutNum(pObj) == 0 )
|
||||
continue;
|
||||
pObj->pCopy = Abc_NtkCreateNode( pNtkNew );
|
||||
pObj->pCopy->pCopy = pObj;
|
||||
}
|
||||
// make latches point to the latch fanins
|
||||
Abc_NtkForEachLatch( pNtk, pObj, i )
|
||||
{
|
||||
assert( !Abc_ObjIsLatch(Abc_ObjFanin0(pObj)) );
|
||||
pObj->pCopy = Abc_ObjFanin0(pObj)->pCopy;
|
||||
}
|
||||
|
||||
// create internal AND nodes w/o strashing for each logic node (including constants)
|
||||
Abc_NtkForEachNode( pNtk, pObj, i )
|
||||
{
|
||||
if ( Abc_ObjFaninNum(pObj) == 0 && Abc_ObjFanoutNum(pObj) == 0 )
|
||||
continue;
|
||||
// get the SOP of the node
|
||||
if ( Abc_NtkHasMapping(pNtk) )
|
||||
pSop = Mio_GateReadSop(pObj->pData);
|
||||
else
|
||||
pSop = pObj->pData;
|
||||
pFanin = Seq_NodeRetimeDerive( pNtkNew, pObj, pSop );
|
||||
Abc_ObjAddFanin( pObj->pCopy, pFanin );
|
||||
Abc_ObjAddFanin( pObj->pCopy, pFanin );
|
||||
}
|
||||
// connect the POs
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
Abc_ObjAddFanin( pObj->pCopy, Abc_ObjFanin0(pObj)->pCopy );
|
||||
|
||||
// start the storage for initial states
|
||||
p = pNtkNew->pManFunc;
|
||||
Seq_Resize( p, Abc_NtkObjNumMax(pNtkNew) );
|
||||
|
||||
// add the sequential edges
|
||||
Abc_NtkForEachLatch( pNtk, pObj, i )
|
||||
Abc_ObjForEachFanout( pObj, pFanout, k )
|
||||
{
|
||||
if ( pObj->pCopy == Abc_ObjFanin0(pFanout->pCopy) )
|
||||
{
|
||||
Seq_NodeInsertFirst( pFanout->pCopy, 0, Abc_LatchInit(pObj) );
|
||||
Seq_NodeInsertFirst( pFanout->pCopy, 1, Abc_LatchInit(pObj) );
|
||||
continue;
|
||||
}
|
||||
Seq_NodeAddEdges_rec( pObj->pCopy, Abc_ObjFanin0(pFanout->pCopy), Abc_LatchInit(pObj) );
|
||||
}
|
||||
|
||||
// collect the nodes in the topological order
|
||||
p->vMapAnds = Abc_NtkDfs( pNtk, 0 );
|
||||
p->vMapCuts = Vec_VecStart( Vec_PtrSize(p->vMapAnds) );
|
||||
p->vMapDelays = Vec_VecStart( Vec_PtrSize(p->vMapAnds) );
|
||||
Vec_PtrForEachEntry( p->vMapAnds, pObj, i )
|
||||
{
|
||||
// change the node to be the new one
|
||||
Vec_PtrWriteEntry( p->vMapAnds, i, pObj->pCopy );
|
||||
// collect the new fanins of this node
|
||||
Abc_ObjForEachFanin( pObj, pFanin, k )
|
||||
Vec_VecPush( p->vMapCuts, i, (void *)( (pFanin->pCopy->Id << 8) | Abc_ObjIsLatch(pFanin) ) );
|
||||
// collect the delay info
|
||||
if ( !Abc_NtkHasMapping(pNtk) )
|
||||
{
|
||||
Abc_ObjForEachFanin( pObj, pFanin, k )
|
||||
Vec_VecPush( p->vMapDelays, i, (void *)Abc_Float2Int(1.0) );
|
||||
}
|
||||
else
|
||||
{
|
||||
Mio_Pin_t * pPin = Mio_GateReadPins(pObj->pData);
|
||||
float Max, tDelayBlockRise, tDelayBlockFall;
|
||||
Abc_ObjForEachFanin( pObj, pFanin, k )
|
||||
{
|
||||
tDelayBlockRise = (float)Mio_PinReadDelayBlockRise( pPin );
|
||||
tDelayBlockFall = (float)Mio_PinReadDelayBlockFall( pPin );
|
||||
Max = ABC_MAX( tDelayBlockRise, tDelayBlockFall );
|
||||
Vec_VecPush( p->vMapDelays, i, (void *)Abc_Float2Int(Max) );
|
||||
pPin = Mio_PinReadNext(pPin);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// set the cutset composed of latch drivers
|
||||
// Abc_NtkAigCutsetCopy( pNtk );
|
||||
// Seq_NtkLatchGetEqualFaninNum( pNtkNew );
|
||||
|
||||
// convert the network back into BDDs if this is how it was
|
||||
if ( fHasBdds )
|
||||
Abc_NtkSopToBdd(pNtk);
|
||||
|
||||
// copy EXDC and check correctness
|
||||
if ( pNtk->pExdc )
|
||||
fprintf( stdout, "Warning: EXDC is not copied when converting to sequential AIG.\n" );
|
||||
if ( !Abc_NtkCheck( pNtkNew ) )
|
||||
fprintf( stdout, "Seq_NtkRetimeDerive(): Network check has failed.\n" );
|
||||
return pNtkNew;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Add sequential edges.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_NodeAddEdges_rec( Abc_Obj_t * pGoal, Abc_Obj_t * pNode, Abc_InitType_t Init )
|
||||
{
|
||||
Abc_Obj_t * pFanin;
|
||||
assert( !Abc_ObjIsLatch(pNode) );
|
||||
if ( !Abc_NodeIsAigAnd(pNode) )
|
||||
return;
|
||||
// consider the first fanin
|
||||
pFanin = Abc_ObjFanin0(pNode);
|
||||
if ( pFanin->pCopy == NULL ) // internal node
|
||||
Seq_NodeAddEdges_rec( pGoal, pFanin, Init );
|
||||
else if ( pFanin == pGoal )
|
||||
Seq_NodeInsertFirst( pNode, 0, Init );
|
||||
// consider the second fanin
|
||||
pFanin = Abc_ObjFanin1(pNode);
|
||||
if ( pFanin->pCopy == NULL ) // internal node
|
||||
Seq_NodeAddEdges_rec( pGoal, pFanin, Init );
|
||||
else if ( pFanin == pGoal )
|
||||
Seq_NodeInsertFirst( pNode, 1, Init );
|
||||
}
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Strashes one logic node using its SOP.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Obj_t * Seq_NodeRetimeDerive( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pRoot, char * pSop )
|
||||
{
|
||||
Dec_Graph_t * pFForm;
|
||||
Dec_Node_t * pNode;
|
||||
Abc_Obj_t * pAnd;
|
||||
int i, nFanins;
|
||||
|
||||
// get the number of node's fanins
|
||||
nFanins = Abc_ObjFaninNum( pRoot );
|
||||
assert( nFanins == Abc_SopGetVarNum(pSop) );
|
||||
if ( nFanins < 2 )
|
||||
{
|
||||
if ( Abc_SopIsConst1(pSop) )
|
||||
return Abc_NtkConst1(pNtkNew);
|
||||
else if ( Abc_SopIsConst0(pSop) )
|
||||
return Abc_ObjNot( Abc_NtkConst1(pNtkNew) );
|
||||
else if ( Abc_SopIsBuf(pSop) )
|
||||
return Abc_ObjFanin0(pRoot)->pCopy;
|
||||
else if ( Abc_SopIsInv(pSop) )
|
||||
return Abc_ObjNot( Abc_ObjFanin0(pRoot)->pCopy );
|
||||
assert( 0 );
|
||||
return NULL;
|
||||
}
|
||||
|
||||
// perform factoring
|
||||
pFForm = Dec_Factor( pSop );
|
||||
// collect the fanins
|
||||
Dec_GraphForEachLeaf( pFForm, pNode, i )
|
||||
pNode->pFunc = Abc_ObjFanin(pRoot,i)->pCopy;
|
||||
// perform strashing
|
||||
pAnd = Dec_GraphToNetworkNoStrash( pNtkNew, pFForm );
|
||||
Dec_GraphFree( pFForm );
|
||||
return pAnd;
|
||||
}
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Reconstructs the network after retiming.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Ntk_t * Seq_NtkRetimeReconstruct( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtkSeq )
|
||||
{
|
||||
Abc_Seq_t * p = pNtkSeq->pManFunc;
|
||||
Abc_Ntk_t * pNtkNew;
|
||||
Abc_Obj_t * pObj, * pObjNew, * pFanin, * pFaninNew;
|
||||
int i, k;
|
||||
|
||||
assert( !Abc_NtkIsSeq(pNtkOld) );
|
||||
assert( Abc_NtkIsSeq(pNtkSeq) );
|
||||
|
||||
// transfer the pointers pNtkOld->pNtkSeq from pCopy to pNext
|
||||
Abc_NtkForEachObj( pNtkOld, pObj, i )
|
||||
pObj->pNext = pObj->pCopy;
|
||||
|
||||
// start the final network
|
||||
pNtkNew = Abc_NtkStartFrom( pNtkSeq, pNtkOld->ntkType, pNtkOld->ntkFunc );
|
||||
|
||||
// copy the internal nodes of the old network into the new network
|
||||
// transfer the pointers pNktOld->pNtkNew to pNtkSeq->pNtkNew
|
||||
Abc_NtkForEachNode( pNtkOld, pObj, i )
|
||||
{
|
||||
if ( i == 0 ) continue;
|
||||
Abc_NtkDupObj( pNtkNew, pObj );
|
||||
pObj->pNext->pCopy = pObj->pCopy;
|
||||
}
|
||||
|
||||
// share the latches
|
||||
Seq_NtkShareLatches( pNtkNew, pNtkSeq );
|
||||
|
||||
// connect the objects
|
||||
Abc_NtkForEachNode( pNtkOld, pObj, i )
|
||||
Abc_ObjForEachFanin( pObj, pFanin, k )
|
||||
{
|
||||
pFaninNew = Seq_EdgeReconstruct_rec( pFanin->pNext, pObj->pNext );
|
||||
assert( pFaninNew != NULL );
|
||||
Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
|
||||
}
|
||||
|
||||
// connect the POs
|
||||
Abc_NtkForEachPo( pNtkOld, pObj, i )
|
||||
{
|
||||
pFaninNew = Seq_EdgeReconstructPO( pObj->pNext );
|
||||
assert( pFaninNew != NULL );
|
||||
Abc_ObjAddFanin( pObj->pNext->pCopy, pFaninNew );
|
||||
}
|
||||
|
||||
// clean the result of latch sharing
|
||||
Seq_NtkShareLatchesClean( pNtkSeq );
|
||||
|
||||
// add the latches and their names
|
||||
Abc_NtkAddDummyLatchNames( pNtkNew );
|
||||
Abc_NtkForEachLatch( pNtkNew, pObjNew, i )
|
||||
{
|
||||
Vec_PtrPush( pNtkNew->vCis, pObjNew );
|
||||
Vec_PtrPush( pNtkNew->vCos, pObjNew );
|
||||
}
|
||||
// fix the problem with complemented and duplicated CO edges
|
||||
Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
|
||||
if ( !Abc_NtkCheck( pNtkNew ) )
|
||||
fprintf( stdout, "Seq_NtkRetimeReconstruct(): Network check has failed.\n" );
|
||||
return pNtkNew;
|
||||
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Reconstructs the network after retiming.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Obj_t * Seq_EdgeReconstruct_rec( Abc_Obj_t * pGoal, Abc_Obj_t * pNode )
|
||||
{
|
||||
Seq_Lat_t * pRing;
|
||||
Abc_Obj_t * pFanin, * pRes = NULL;
|
||||
|
||||
if ( !Abc_NodeIsAigAnd(pNode) )
|
||||
return NULL;
|
||||
|
||||
// consider the first fanin
|
||||
pFanin = Abc_ObjFanin0(pNode);
|
||||
if ( pFanin->pCopy == NULL ) // internal node
|
||||
pRes = Seq_EdgeReconstruct_rec( pGoal, pFanin );
|
||||
else if ( pFanin == pGoal )
|
||||
{
|
||||
if ( pRing = Seq_NodeGetRing( pNode, 0 ) )
|
||||
pRes = pRing->pLatch;
|
||||
else
|
||||
pRes = pFanin->pCopy;
|
||||
}
|
||||
if ( pRes != NULL )
|
||||
return pRes;
|
||||
|
||||
// consider the second fanin
|
||||
pFanin = Abc_ObjFanin1(pNode);
|
||||
if ( pFanin->pCopy == NULL ) // internal node
|
||||
pRes = Seq_EdgeReconstruct_rec( pGoal, pFanin );
|
||||
else if ( pFanin == pGoal )
|
||||
{
|
||||
if ( pRing = Seq_NodeGetRing( pNode, 1 ) )
|
||||
pRes = pRing->pLatch;
|
||||
else
|
||||
pRes = pFanin->pCopy;
|
||||
}
|
||||
return pRes;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Reconstructs the network after retiming.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Abc_Obj_t * Seq_EdgeReconstructPO( Abc_Obj_t * pNode )
|
||||
{
|
||||
Seq_Lat_t * pRing;
|
||||
assert( Abc_ObjIsPo(pNode) );
|
||||
if ( pRing = Seq_NodeGetRing( pNode, 0 ) )
|
||||
return pRing->pLatch;
|
||||
else
|
||||
return Abc_ObjFanin0(pNode)->pCopy;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
|
@ -49,7 +49,7 @@ static void Seq_NodePrintInfoPlus( Abc_Obj_t * pNode );
|
|||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose )
|
||||
int Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Abc_Seq_t * p = pNtk->pManFunc;
|
||||
Abc_Obj_t * pNode;
|
||||
|
|
@ -76,7 +76,7 @@ void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
|
|||
if ( Delta == 0.0 )
|
||||
{
|
||||
printf( "Cannot retime/map if the library does not have NAND2 or AND2.\n" );
|
||||
return;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
// get the upper bound on the clock period
|
||||
|
|
@ -90,8 +90,14 @@ void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
|
|||
}
|
||||
|
||||
// make sure this clock period is feasible
|
||||
assert( Seq_NtkMappingForPeriod( pNtk, FiMax, fVerbose ) );
|
||||
|
||||
if ( !Seq_NtkMappingForPeriod( pNtk, FiMax, fVerbose ) )
|
||||
{
|
||||
printf( "Error: The upper bound on the clock period cannot be computed.\n" );
|
||||
printf( "The reason for this error may be the presence in the circuit of logic\n" );
|
||||
printf( "that is not reachable from the PIs. Mapping/retiming is not performed.\n" );
|
||||
return 0;
|
||||
}
|
||||
|
||||
// search for the optimal clock period between 0 and nLevelMax
|
||||
FiBest = Seq_NtkMappingSearch_rec( pNtk, 0.0, FiMax, Delta, fVerbose );
|
||||
|
||||
|
|
@ -99,6 +105,11 @@ void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
|
|||
RetValue = Seq_NtkMappingForPeriod( pNtk, FiBest, fVerbose );
|
||||
assert( RetValue );
|
||||
|
||||
// fix the problem with non-converged delays
|
||||
Vec_PtrForEachEntry( p->vMapAnds, pNode, i )
|
||||
if ( Seq_NodeGetLValueP(pNode) < -ABC_INFINITY/2 )
|
||||
Seq_NodeSetLValueP( pNode, 0 );
|
||||
|
||||
// experiment by adding an epsilon to all LValues
|
||||
// Vec_PtrForEachEntry( p->vMapAnds, pNode, i )
|
||||
// Seq_NodeSetLValueP( pNode, Seq_NodeGetLValueP(pNode) - p->fEpsilon );
|
||||
|
|
@ -126,8 +137,18 @@ void Seq_NtkRetimeDelayLags( Abc_Ntk_t * pNtkOld, Abc_Ntk_t * pNtk, int fVerbose
|
|||
// print the result
|
||||
if ( fVerbose )
|
||||
printf( "The best clock period is %6.2f.\n", FiBest );
|
||||
|
||||
/*
|
||||
{
|
||||
FILE * pTable;
|
||||
pTable = fopen( "stats.txt", "a+" );
|
||||
fprintf( pTable, "%s ", pNtk->pName );
|
||||
fprintf( pTable, "%.2f ", FiBest );
|
||||
fprintf( pTable, "\n" );
|
||||
fclose( pTable );
|
||||
}
|
||||
*/
|
||||
// Seq_NodePrintInfo( Abc_NtkObj(pNtk, 847) );
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
|
|
|||
|
|
@ -461,6 +461,134 @@ int Seq_MapComputeAreaFlows( Abc_Ntk_t * pNtk, int fVerbose )
|
|||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Collects all the internal nodes reachable from POs.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_NtkReachNodesFromPos_rec( Abc_Obj_t * pAnd, Vec_Ptr_t * vNodes )
|
||||
{
|
||||
// skip if this is a non-PI node
|
||||
if ( !Abc_NodeIsAigAnd(pAnd) )
|
||||
return;
|
||||
// skip a visited node
|
||||
if ( Abc_NodeIsTravIdCurrent(pAnd) )
|
||||
return;
|
||||
Abc_NodeSetTravIdCurrent(pAnd);
|
||||
// visit the fanin nodes
|
||||
Seq_NtkReachNodesFromPos_rec( Abc_ObjFanin0(pAnd), vNodes );
|
||||
Seq_NtkReachNodesFromPos_rec( Abc_ObjFanin1(pAnd), vNodes );
|
||||
// add this node
|
||||
Vec_PtrPush( vNodes, pAnd );
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Collects all the internal nodes reachable from POs.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
void Seq_NtkReachNodesFromPis_rec( Abc_Obj_t * pAnd, Vec_Ptr_t * vNodes )
|
||||
{
|
||||
Abc_Obj_t * pFanout;
|
||||
int k;
|
||||
// skip if this is a non-PI node
|
||||
if ( !Abc_NodeIsAigAnd(pAnd) )
|
||||
return;
|
||||
// skip a visited node
|
||||
if ( Abc_NodeIsTravIdCurrent(pAnd) )
|
||||
return;
|
||||
Abc_NodeSetTravIdCurrent(pAnd);
|
||||
// visit the fanin nodes
|
||||
Abc_ObjForEachFanout( pAnd, pFanout, k )
|
||||
Seq_NtkReachNodesFromPis_rec( pFanout, vNodes );
|
||||
// add this node
|
||||
Vec_PtrPush( vNodes, pAnd );
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Collects all the internal nodes reachable from POs.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
Vec_Ptr_t * Seq_NtkReachNodes( Abc_Ntk_t * pNtk, int fFromPos )
|
||||
{
|
||||
Vec_Ptr_t * vNodes;
|
||||
Abc_Obj_t * pObj, * pFanout;
|
||||
int i, k;
|
||||
assert( Abc_NtkIsSeq(pNtk) );
|
||||
vNodes = Vec_PtrAlloc( 1000 );
|
||||
Abc_NtkIncrementTravId( pNtk );
|
||||
if ( fFromPos )
|
||||
{
|
||||
// traverse the cone of each PO
|
||||
Abc_NtkForEachPo( pNtk, pObj, i )
|
||||
Seq_NtkReachNodesFromPos_rec( Abc_ObjFanin0(pObj), vNodes );
|
||||
}
|
||||
else
|
||||
{
|
||||
// tranvers the reverse cone of the constant node
|
||||
pObj = Abc_NtkConst1( pNtk );
|
||||
Abc_ObjForEachFanout( pObj, pFanout, k )
|
||||
Seq_NtkReachNodesFromPis_rec( pFanout, vNodes );
|
||||
// tranvers the reverse cone of the PIs
|
||||
Abc_NtkForEachPi( pNtk, pObj, i )
|
||||
Abc_ObjForEachFanout( pObj, pFanout, k )
|
||||
Seq_NtkReachNodesFromPis_rec( pFanout, vNodes );
|
||||
}
|
||||
return vNodes;
|
||||
}
|
||||
|
||||
/**Function*************************************************************
|
||||
|
||||
Synopsis [Perform sequential cleanup.]
|
||||
|
||||
Description []
|
||||
|
||||
SideEffects []
|
||||
|
||||
SeeAlso []
|
||||
|
||||
***********************************************************************/
|
||||
int Seq_NtkCleanup( Abc_Ntk_t * pNtk, int fVerbose )
|
||||
{
|
||||
Vec_Ptr_t * vNodesPo, * vNodesPi;
|
||||
int Counter = 0;
|
||||
assert( Abc_NtkIsSeq(pNtk) );
|
||||
// collect the nodes reachable from POs and PIs
|
||||
vNodesPo = Seq_NtkReachNodes( pNtk, 1 );
|
||||
vNodesPi = Seq_NtkReachNodes( pNtk, 0 );
|
||||
printf( "Total nodes = %6d. Reachable from POs = %6d. Reachable from PIs = %6d.\n",
|
||||
Abc_NtkNodeNum(pNtk), Vec_PtrSize(vNodesPo), Vec_PtrSize(vNodesPi) );
|
||||
if ( Abc_NtkNodeNum(pNtk) > Vec_PtrSize(vNodesPo) )
|
||||
{
|
||||
Counter = Abc_NtkReduceNodes( pNtk, vNodesPo );
|
||||
if ( fVerbose )
|
||||
printf( "Cleanup removed %d nodes that are not reachable from the POs.\n", Counter );
|
||||
}
|
||||
Vec_PtrFree( vNodesPo );
|
||||
Vec_PtrFree( vNodesPi );
|
||||
return Counter;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
/// END OF FILE ///
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
Loading…
Reference in New Issue