From e384c5b62d7e60e1db9793dac9a9542b4428b33d Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 16 Nov 2023 12:06:40 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/User-Documentation.md b/User-Documentation.md index ab5d63b..de65798 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -69,7 +69,7 @@ After main wishbone port are the **second-wishbone ports**. This interface is on Next are the **DDR3 I/O ports**, these will be connected directly to the top-level pins of your design thus port-names must match what is indicated on your constraint file. You do not need to understand what each DDR3 I/O ports does but if you're curious, details on each DDR3 I/O pins are described on _2.10 Pinout Description_ from [JEDEC DDR3 doc (page 13)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf). -Finally are the debug ports, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored. +Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored. ## Connecting to Top-Level DDR3 I/O Pins