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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-16 12:16:21 +08:00
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User-Documentation.md

@ -72,8 +72,8 @@ Next are the **DDR3 I/O ports**, these will be connected directly to the top-lev
Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored.
## Connecting to Top-Level DDR3 I/O Pins
## Constraint File
Example of constraint file is from the [Kintex Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389), highlighted are all the DDR3 pins.
### Note:
[1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.