From e12fe49d4228d75ccc16c0f8b2d2f9502b8ab364 Mon Sep 17 00:00:00 2001
From: Angelo Jacobo <jacobo.angeloECE@gmail.com>
Date: Thu, 16 Nov 2023 12:16:21 +0800
Subject: [PATCH] Updated User Documentation (markdown)

---
 User-Documentation.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/User-Documentation.md b/User-Documentation.md
index 348923a..33ab1d6 100644
--- a/User-Documentation.md
+++ b/User-Documentation.md
@@ -72,8 +72,8 @@ Next are the **DDR3 I/O ports**, these will be connected directly to the top-lev
 
 Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored.
 
-## Connecting to Top-Level DDR3 I/O Pins
-
+## Constraint File
+Example of constraint file is from the [Kintex Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/kintex_switch_files/kluster.xdc#L227-L389), highlighted are all the DDR3 pins.
 
 ### Note:  
 [1]: For x16 DDR3 like in Arty S7, use `DQ_BITS` of 8 and `LANES` of 2.