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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-15 17:07:37 +08:00
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User-Documentation.md

@ -5,7 +5,7 @@ The goal of this documentation is to enable smooth transition when using this DD
# Getting Started
The recommended way to instantiate this IP is to use the top module `rtl/ddr3_top.v`, a template for instantiation is also included in that file. The first thing to edit are the parameters:
The recommended way to instantiate this IP is to use the top module `rtl/ddr3_top.v`, a template for instantiation is also included in that file. The first thing to edit are the **top-level parameters**:
| Parameter | Function |
| :---: | :--- |
@ -27,7 +27,7 @@ The recommended way to instantiate this IP is to use the top module `rtl/ddr3_to
| SECOND_WISHBONE | set to 1 if 2nd wishbone for debugging is needed , otherwise 0.|
After the parameters, connect the ports of the top module to your design. Below are the ports for clocks and reset:
After the parameters, connect the ports of the top module to your design. Below are the **ports for clocks and reset**:
| Ports | Function |
| :---: | :--- |
| i_controller_clk | clock of the controller interface with period of `CONTROLLER_CLK_PERIOD` |
@ -37,7 +37,7 @@ After the parameters, connect the ports of the top module to your design. Below
| i_rst_n | Active-low synchronous reset for the entire DDR3 controller and PHY |
Below are the main wishbone ports:
Below are the **main wishbone ports**:
| Ports | Function |
| :---: | :--- |
@ -51,11 +51,11 @@ Below are the main wishbone ports:
| o_wb_ack | Acknowledgement signal. Indicates that a read or write request has been completed. |
| o_wb_data | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`.
Auxiliary ports associated to the main wishbone ports:
Below are the **auxiliary ports** associated with the main wishbone. This is not required for normal operation, but is intended for AXI-interface compatibility *which is not yet available*:
| Ports | Function |
| :---: | :--- |
| i_aux | Request ID line for AXI-interface compatibility with width of `AUX_WIDTH`. The Request ID is retrieved simultaneously with the strobe request. |
| o_aux | Request ID line for AXI-interface compatibility with width of `AUX_WIDTH`. The Request ID is sent back concurrently with the acknowledgement signal. |
| i_aux | Request ID line with width of `AUX_WIDTH`. The Request ID is retrieved simultaneously with the strobe request. |
| o_aux | Request ID line with width of `AUX_WIDTH`. The Request ID is sent back concurrently with the acknowledgement signal. |
**Note:**