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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-15 16:56:42 +08:00
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User-Documentation.md

@ -16,6 +16,7 @@ The recommended way to instantiate this IP is to use the top module `rtl/ddr3_to
| BA_BITS | width of bank address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Usual value is `3`. |
| DQ_BITS | device width. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values are `4`, `8`, or `16`. [1] |
| LANES | number of DDR3 device to be controlled. This depends on the DDR3 module used. [1] |
| AUX_WIDTH | width of auxiliary line. Value must be >= 4. |
| WB2_ADDR_BITS | width of 2nd wishbone address bus for debugging (only relevant if SECOND_WISHBONE = 1). |
| WB2_DATA_BITS | width of 2nd wishbone data bus for debugging (only relevant if SECOND_WISHBONE = 1). |
| OPT_LOWPOWER | _has no effect yet_ |
@ -44,15 +45,17 @@ Below are the main wishbone ports:
| i_wb_stb | Strobe or transfer request signal. It's asserted (set to 1) to request a data transfer. |
| i_wb_we | Write-enable signal. A high value (1) indicates a write operation, and a low value (0) indicates a read operation. |
| i_wb_addr | Address bus. Used to specify the address for the current read or write operation. Formatted as {row, bank, column}. |
| i_wb_data | Data bus for write operations. In a 4:1 controller, the data width is 8 times the DDR3 pins `DQ_BITS`x`LANES`. |
| i_wb_data | Data bus for write operations. In a 4:1 controller, the data width is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`. |
| i_wb_sel | Byte select for write operations. Indicates which bytes of the data bus are to be overwritten for the write operation. |
| o_wb_stall | Indicates if the controller is busy (1)and cannot accept any new requests. |
| o_wb_ack | Acknowledgement signal. Indicates that a read or write request has been completed. |
| o_wb_data | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `DQ_BITS`x`LANES`.
Extra ports associated to the main wishbone ports:
| i_wb_data | Data bus for write operations. In a 4:1 controller, the data width is 8 times the DDR3 pins `DQ_BITS`x`LANES`. |
| o_wb_data | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`.
Auxiliary ports associated to the main wishbone ports:
| Ports | Function |
| :---: | :--- |
| i_aux | Request ID line for AXI-interface compatibility with width of `AUX_WIDTH`. The Request ID is retrieved simultaneously with the strobe request. |
| o_aux | Request ID line for AXI-interface compatibility with width of `AUX_WIDTH`. The Request ID is sent back concurrently with the acknowledgement signal. |
**Note:**