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Updated User Documentation (markdown)

Angelo Jacobo 2023-11-26 11:45:48 +08:00
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User-Documentation.md

@ -111,6 +111,9 @@ Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/e
# Simulation # Simulation
For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=%7B%22term%22%3A%22DDR3%20model%22%7D) is used.
Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks: Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks:
![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d) ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d)