From 82113aa1b712a92b4fa8d0cfa3f2c60bc80d0a4f Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sun, 26 Nov 2023 11:45:48 +0800 Subject: [PATCH] Updated User Documentation (markdown) --- User-Documentation.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/User-Documentation.md b/User-Documentation.md index 294588f..15ce1db 100644 --- a/User-Documentation.md +++ b/User-Documentation.md @@ -111,6 +111,9 @@ Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/e # Simulation + +For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=%7B%22term%22%3A%22DDR3%20model%22%7D) is used. + Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado then run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks: ![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d)