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UberDDR3
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Opensource DDR3 Controller
25 Commits 6 Branches 0 Tags 97 MiB
Verilog 58.7%
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Angelo Jacobo fec8b5b3fc
Update ddr3_controller.v 		2023-04-06 19:01:02 +08:00
rtl Update ddr3_controller.v 2023-04-06 19:01:02 +08:00
LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-04-06 17:54:16 +08:00
ddr3_controller.sby removed parameter file "ddr3_parameters.vh" 2023-03-09 18:16:01 +08:00
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README.md

DDR3_Controller

🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧

Sequential Read

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Sequential Read then Sequential Write

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