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UberDDR3
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UberDDR3/testbench/ARTY_S7
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AngeloJacobo fd443ddefd add wb2 width 2023-08-20 13:23:48 +08:00
..
verilog-uart@1363dc7678 added uart submodule 2023-08-17 11:36:15 +08:00
arty_ddr3.v add wb2 width 2023-08-20 13:23:48 +08:00
arty_ddr3_v1.bit added working bitfiles for arty s7 2023-08-20 11:20:41 +08:00
arty_ddr3_v1.ltx added working bitfiles for arty s7 2023-08-20 11:20:41 +08:00
arty_ddr3_v2.bit added working bitfiles for arty s7 2023-08-20 11:20:41 +08:00
arty_ddr3_v2.ltx added working bitfiles for arty s7 2023-08-20 11:20:41 +08:00