Opensource DDR3 Controller
Go to file
Angelo Jacobo fd09ce2ed9
Update README.md
2023-04-27 19:48:59 +08:00
rtl added read phy interface 2023-04-27 19:40:35 +08:00
LICENSE changed license to Apache 2.0 2023-03-23 20:18:46 +08:00
README.md Update README.md 2023-04-27 19:48:59 +08:00
ddr3_controller.sby removed parameter file "ddr3_parameters.vh" 2023-03-09 18:16:01 +08:00
formal_cover.gtkw Add files via upload 2023-04-06 19:45:09 +08:00
run.sh include directory on iverilog command 2023-03-02 20:20:14 +08:00

README.md

DDR3_Controller

🚧 👷‍♂️ 👷‍♂️ UNDER CONSTRUCTION 👷‍♂️ 👷‍♂️ 🚧

Sequential Read

image

Sequential Read then Sequential Write

image

Random Access

image

Sequential Read Until Next Bank

image

PHY Interface

WRITE OPERATION

image

Sequential Write

image

BITSLIP_DQS_TRAIN STATE:

image