Angelo Jacobo f648035e4e added phy interface (separated from controller)		2023-05-28 16:19:47 +08:00
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DDR3 SDRAM Verilog Model	readme file from Micron	2023-05-28 16:14:21 +08:00
ddr3_controller.v	include only the controller (phy is now a separate module)	2023-05-28 16:18:14 +08:00
ddr3_phy.v	added phy interface (separated from controller)	2023-05-28 16:19:47 +08:00
sdram.txt	Add files via upload	2023-05-22 19:53:20 +08:00