1.8 KiB
1.8 KiB
DDR3_Controller
🚧 👷♂️ 👷♂️ UNDER CONSTRUCTION 👷♂️ 👷♂️ 🚧
Sequential Read
Sequential Read then Sequential Write
Random Access
Sequential Read Until Next Bank
PHY Interface
WRITE OPERATION
Sequential Write
BITSLIP_DQS_TRAIN STATE:
MPR_READ STATE:
BITSLIP_DQ_TRAIN STATE:
Sequential Read:
